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Wyszukujesz frazę "Ubar, R." wg kryterium: Autor


Wyświetlanie 1-3 z 3
Tytuł:
Distributed approach for parallel exact critical path tracing fault simulation
Autorzy:
Ivask, E.
Devadze, S.
Ubar, R.
Powiązania:
https://bibliotekanauki.pl/articles/398084.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
systemy rozproszone
symulacja błędów
śledzenie ścieżki krytycznej
cyfrowy test
distributed computing
fault simulation
critical path tracing
digital test
Opis:
Distributed computing attempts to aggregate different computing resources available in enterprises and in the Internet for computation intensive applications in a transparent and scalable way. Fault simulation used in digital design flow for test quality evaluation can require a lot of processor and memory resources. To speed up simulation and to overcome the problem of memory limits in the case of very large circuits, a method of model partitioning and the procedure of parallel reasoning for several distributed simulation agents was proposed. The concept and implementation of web-based distributed system was introduced.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 2; 165-174
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Automated software-based in-field self-test program synthesis
Autorzy:
Jasnetski, A.
Ubar, R.
Tsertov, A
Powiązania:
https://bibliotekanauki.pl/articles/397877.pdf
Data publikacji:
2017
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
microprocessor
software based self-test
SBST
automatic test program generation
high-level decision diagrams
HLDD synthesis
mikroprocesor
programy ATPG
HLDD
synteza HLDD
Opis:
This paper presents a methodology to automate functional Software-Based Self-Test program development. We rely on the previously published research on modeling processors using subclass of acyclic directed graphs called High-Level Decision Diagrams (HLDD). The HLDD model of the processor gets generated from its Instruction Set Architecture. The HLDD model is then used together with beforehand prepared assembly program templates in the generation of the complete self-test program. The research presented in this paper includes examples of test generation for the 32-bit SPARCv8 microprocessor Leon 3. The experimental results demonstrate that automatically generated SBST program obtains comparable to the state-of the art fault coverage data.
Źródło:
International Journal of Microelectronics and Computer Science; 2017, 8, 2; 57-64
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Open-Source JTAG Simulator Bundle for Labs
Autorzy:
Shibin, K.
Devadze, S.
Rosin, V.
Jutman, A.
Ubar, R.
Powiązania:
https://bibliotekanauki.pl/articles/227122.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
JTAG
boundary scan
IEEE 1149.1
Trainer 1149
goJTAG
Opis:
This paper presents a software/hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips and non-BS clusters. It provides the user with a full flexibility in working with any type of BS structures by supporting standard formats such as Boundary Scan Description Language and SVF (for defining test patterns). A special fault simulation mode allows injecting various types of interconnection faults to simulate their impact and inspect them using interactive tools. Trainer 1149 is the main component of a recent goJTAG initiative that aims at bringing JTAG tools closer to the user for both learning and experimental work purposes. The software part is implemented in multi-platform Java environment and distributed as an open-source freeware. Using a convenient low-cost USB-JTAG controller, one can also test real defects in real hardware. Such combination of features is unique for a public domain BS package.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 3; 233-239
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

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