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Wyszukujesz frazę "Trifiletti, A." wg kryterium: Autor

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    Wyświetlanie 1-3 z 3
    Tytuł:
    An efficient synthesis-oriented CAD implementation of Nyquist stability criterion
    Autorzy:
    Centurelli, F.
    Luzzi, R.
    Scotti, G.
    Tommasino, P.
    Trifiletti, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/378419.pdf
    Data publikacji:
    2002
    Wydawca:
    Sieć Badawcza Łukasiewicz - Instytut Technologii Elektronowej
    Opis:
    Nyquist stability criterion is largely used to determine the number of Right-Half Plane poles of feedback systems and circuits. However, visual inspection of open-loop gain polar plot is required, and automatic stability check within microwave CAD tools is not possible. In this paper, a procedure to check system and circuit linear stability by means of Nyquist criterion within CAD tools, is presented. The proposed method makes use of integral phase evaluation of a transfer function, and does not require visual inspection of Nyquist plots. The method has been successfully implemented in commercial microwave CAD tools.
    Źródło:
    Electron Technology : Internet Journal; 2001-2002, 34, 2; 1-5
    1897-2381
    Pojawia się w:
    Electron Technology : Internet Journal
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A power-balanced sequential element for the delay-based dual-rail precharge logic style
    Autorzy:
    Bongiovanni, S
    Olivieri, M
    Scotti, G.
    Trifiletti, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/397742.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    cryptography
    delay-based dual-rail precharge logic
    DDPL
    dynamic flip-flop
    dual-rail precharge logic
    power analysis
    PA
    power-balanced circuits
    sense amplifier-based logic
    SABL
    VLSI design
    VLSI
    kryptografia
    przerzutnik dynamiczny
    analiza energetyczna
    Opis:
    Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is to break the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave flip-flop which is compatible with the DDPL data encoding. Efforts were made in order to design a completely dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover we show that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performance in terms of NED (Normalized Energy Deviation) and CV (Coefficient of Variation) of the current samples as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant flip-flops in the real case of unbalanced load conditions.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2013, 4, 4; 129-141
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On-chip current-mode approach to thwart CPA attacks in CMOS nanometer technology
    Autorzy:
    Bellizia, D.
    Scotti, G.
    Trifiletti, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/398086.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    IoT
    internet of things (IoT)
    Power Analysis Attacks
    smart card
    CPA
    current-mode
    Side Channel Analysis
    CMOS
    Cryptography
    PRESENT
    Internet rzeczy
    karta inteligentna
    moduły prądowe
    kryptografia
    Opis:
    The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition to that, designers have to deal with demanding requirements, since those smart devices require stringent area and energy constraints. In this work, a novel analog-level approach to counteract PAA is presented, taking benefits of the current-mode approach. The kernel of this approach is that the information leakage exploited in a PAA is leaked through current absorption of a cryptographic device. Thanks to an on-chip measuring of the current absorbed by the cryptographic logic, it is possible to generate an error signal. Throughout a current-mode feedback mechanism, the data-dependent component of the overall consumption can be compensated, making the energy requirement constant at any cycle and thwarting the possibility to recover sensible information. Two possible implementations of the proposed approach are presented in this work and their effectiveness has been evaluated using a 40nm CMOS design library. The proposed approach is able to increase the Measurements to Disclosure (MTD) of at least three orders of magnitude, comparing to the unprotected implementation. It has to be pointed out that the on-chip current-mode suppressor, based on the proposed approach, is able to provide a very good security performance, while requiring a very small overhead in terms of silicon area (xl.007) and power consumption (xl.07).
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 4; 147-156
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-3 z 3

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