- Tytuł:
- Challenges for 10 nm MOSFET process integration
- Autorzy:
-
Östling, M.
Malm, B. G.
Haartman, M.
Hallstedt, J.
Zhang, Z.
Hellström, P. E.
Zhang, S. - Powiązania:
- https://bibliotekanauki.pl/articles/309004.pdf
- Data publikacji:
- 2007
- Wydawca:
- Instytut Łączności - Państwowy Instytut Badawczy
- Tematy:
-
sstrained silicon
silicon-germanium
silicon-on-insulator (SOI)
high-k dielectrics
hafnium oxide
nanowire
low frequency noise
mobility
metal gate - Opis:
- An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.
- Źródło:
-
Journal of Telecommunications and Information Technology; 2007, 2; 25-32
1509-4553
1899-8852 - Pojawia się w:
- Journal of Telecommunications and Information Technology
- Dostawca treści:
- Biblioteka Nauki
Artykuł