Autor: Jasnetski, a - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Automated software-based in-field self-test program synthesis
Autorzy:: Jasnetski, A.
Ubar, R.
Tsertov, A
Powiązania:: https://bibliotekanauki.pl/articles/397877.pdf
Data publikacji:: 2017
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: microprocessor
software based self-test
SBST
automatic test program generation
high-level decision diagrams
HLDD synthesis
mikroprocesor
programy ATPG
HLDD
synteza HLDD
Opis:: This paper presents a methodology to automate functional Software-Based Self-Test program development. We rely on the previously published research on modeling processors using subclass of acyclic directed graphs called High-Level Decision Diagrams (HLDD). The HLDD model of the processor gets generated from its Instruction Set Architecture. The HLDD model is then used together with beforehand prepared assembly program templates in the generation of the complete self-test program. The research presented in this paper includes examples of test generation for the 32-bit SPARCv8 microprocessor Leon 3. The experimental results demonstrate that automatically generated SBST program obtains comparable to the state-of the art fault coverage data.
Źródło:: International Journal of Microelectronics and Computer Science; 2017, 8, 2; 57-64
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: On In-System Programming of Non-volatile Memories
Autorzy:: Tsertov, A
Devadze, S.
Jutman, A
Jasnetski, a
Powiązania:: https://bibliotekanauki.pl/articles/397831.pdf
Data publikacji:: 2013
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: programowanie w systemie
ISP
JTG
pamięć trwała
in-system programming
processor-centric board
JTAG
non-volatile memory
Opis:: With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for comparison of state-of-the-art ISP solutions. The effective comparison pin-points the time losses, that can be eliminated by the use of multiple page buffers. The technique has proven to achieve exceptionally short programming time, which is close to the operational speed limit of modern NVMs. The method is based on the ubiquitous JTAG access bus which makes it applicable for the most board manufacturing strategies despite a slow nature of JTAG bus.
Źródło:: International Journal of Microelectronics and Computer Science; 2013, 4, 2; 72-78
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 3.

Tytuł:: In-system programming of non-volatile memories on microprocessor-centric boards
Autorzy:: Tsertov, A
Devadze, S.
Jutman, A.
Jasnetski, A
Powiązania:: https://bibliotekanauki.pl/articles/397873.pdf
Data publikacji:: 2014
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: in-system programming
processor-centric board
JTAG
non-volatile memory
programowanie w systemie
pamięć nieulotna
Opis:: With the continuous growth of capacity of non-volatile memories (NVM) in-system programming (ISP) has become the most time-consuming step in post-assembly phase of board manufacturing. This paper presents a method to assess ISP solutions for on-chip and on-board NVMs. The major contribution of the approach is the formal basis for evaluation of the state-of-the-art ISP solutions. The proposed comparison pin-points the time losses, that can be eliminated by the use of multiple page buffers. The technique has proven to achieve exceptionally short programming time, which is close to the operational speed limit of modern NVMs. The method is based on the ubiquitous JTAG access bus which makes it applicable for the most board manufacturing strategies despite a slow nature of JTAG bus.
Źródło:: International Journal of Microelectronics and Computer Science; 2014, 5, 1; 25-34
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

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