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Wyszukujesz frazę "Cheng, Kaixing" wg kryterium: Autor


Wyświetlanie 1-2 z 2
Tytuł:
Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity
Autorzy:
Cheng, Kaixing
Luo, Zhongqiang
Xiong, Xingzhong
Wei, Xiaohan
Powiązania:
https://bibliotekanauki.pl/articles/1844520.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
high-speed PCB
signal integrity
equal-length wiring
HyperLynx
Opis:
As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the ”spiral wiring” way and the ”double spiral wiring” way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 3; 385-394
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform
Autorzy:
Wei, Xiaohan
Xiong, Xingzhong
Luo, Zhongqiang
Wang, Jianwu
Cheng, Kaixing
Powiązania:
https://bibliotekanauki.pl/articles/1844640.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
clock synchronization
fronthaul
TSN
system-on-chip
IEEE 1588
Opis:
The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second signals (PPS). The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 2; 289-294
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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