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Wyszukujesz frazę "Borowik, G." wg kryterium: Autor

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    Wyświetlanie 1-8 z 8
    Tytuł:
    A Software Architecture Assisting Workflow Executions on Cloud Resources
    Autorzy:
    Borowik, G.
    Woźniak, M.
    Fornaia, A.
    Giunta, R.
    Napoli, C.
    Pappalardo, G.
    Tramontana, E.
    Powiązania:
    https://bibliotekanauki.pl/articles/226324.pdf
    Data publikacji:
    2015
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    software architecture
    dependability
    workflows
    cloud computing
    monitoring
    Opis:
    An enterprise providing services handled by means of workflows needs to monitor and control their execution, gather usage data, determine priorities, and properly use computing cloud-related resources. This paper proposes a software architecture that connects unaware services to components handling workflow monitoring and management concerns. Moreover, the provided components enhance dependability of services while letting developers focus only on the business logic.
    Źródło:
    International Journal of Electronics and Telecommunications; 2015, 61, 1; 17-22
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Features Reduction Using Logic Minimization Techniques
    Autorzy:
    Borowik, G.
    Łuba, T.
    Zydek, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/227282.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    machine learning
    knowledge representation
    discernibility function
    logic minimization
    attribute reduction
    complement
    Opis:
    This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 1; 71-76
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Optimization on the complementation procedure towards efficient implementation of the index generation function
    Autorzy:
    Borowik, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/330597.pdf
    Data publikacji:
    2018
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    data reduction
    feature selection
    indiscernibility matrix
    logic synthesis
    index generation function
    redukcja danych
    selekcja cech
    synteza logiczna
    funkcja generowania indeksów
    Opis:
    In the era of big data, solutions are desired that would be capable of efficient data reduction. This paper presents a summary of research on an algorithm for complementation of a Boolean function which is fundamental for logic synthesis and data mining. Successively, the existing problems and their proposed solutions are examined, including the analysis of current implementations of the algorithm. Then, methods to speed up the computation process and efficient parallel implementation of the algorithm are shown; they include optimization of data representation, recursive decomposition, merging, and removal of redundant data. Besides the discussion of computational complexity, the paper compares the processing times of the proposed solution with those for the well-known analysis and data mining systems. Although the presented idea is focused on searching for all possible solutions, it can be restricted to finding just those of the smallest size. Both approaches are of great application potential, including proving mathematical theorems, logic synthesis, especially index generation functions, or data processing and mining such as feature selection, data discretization, rule generation, etc. The problem considered is NP-hard, and it is easy to point to examples that are not solvable within the expected amount of time. However, the solution allows the barrier of computations to be moved one step further. For example, the unique algorithm can calculate, as the only one at the moment, all minimal sets of features for few standard benchmarks. Unlike many existing methods, the algorithm additionally works with undetermined values. The result of this research is an easily extendable experimental software that is the fastest among the tested solutions and the data mining systems.
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2018, 28, 4; 803-815
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Application of selected supervised classification methods to bank marketing campaign
    Autorzy:
    Grzonka, D.
    Borowik, B.
    Suchacka, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/94739.pdf
    Data publikacji:
    2016
    Wydawca:
    Szkoła Główna Gospodarstwa Wiejskiego w Warszawie. Wydawnictwo Szkoły Głównej Gospodarstwa Wiejskiego w Warszawie
    Tematy:
    classification
    supervised learning
    data mining
    decision trees
    bagging
    boosting
    random forests
    bank marketing
    R project
    Opis:
    Supervised classification covers a number of data mining methods based on training data. These methods have been successfully applied to solve multi-criteria complex classification problems in many domains, including economical issues. In this paper we discuss features of some supervised classification methods based on decision trees and apply them to the direct marketing campaigns data of a Portuguese banking institution. We discuss and compare the following classification methods: decision trees, bagging, boosting, and random forests. A classification problem in our approach is defined in a scenario where a bank’s clients make decisions about the activation of their deposits. The obtained results are used for evaluating the effectiveness of the classification rules.
    Źródło:
    Information Systems in Management; 2016, 5, 1; 36-48
    2084-5537
    2544-1728
    Pojawia się w:
    Information Systems in Management
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Discretization of data using Boolean transformations and information theory based evaluation criteria
    Autorzy:
    Jankowski, C.
    Reda, D.
    Mańkowski, M.
    Borowik, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/200750.pdf
    Data publikacji:
    2015
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    machine learning
    discretization
    discernibility function
    logic minimization
    information theory
    entropy
    nauczanie maszynowe
    dyskretyzacja
    minimalizacja funkcji logicznych
    teoria informacji
    entropia
    Opis:
    Discretization is one of the most important parts of decision table preprocessing. Transforming continuous values of attributes into discrete intervals influences further analysis using data mining methods. In particular, the accuracy of generated predictions is highly dependent on the quality of discretization. The paper contains a description of three new heuristic algorithms for discretization of numeric data, based on Boolean reasoning. Additionally, an entropy-based evaluation of discretization is introduced to compare the results of the proposed algorithms with the results of leading university software for data analysis. Considering the discretization as a data compression method, the average compression ratio achieved for databases examined in the paper is 8.02 while maintaining the consistency of databases at 100%.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2015, 63, 4; 923-932
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Statechart-based Controllers Synthesis in FPGA Structures with Embedded Array Blocks
    Autorzy:
    Łabiak, G.
    Borowik, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/226148.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    digital controller
    statechart
    FSM
    decomposition
    FPGA
    symbolic methods
    embedded memory
    Opis:
    Statechart diagrams, in general, are visual formalism for description of complex systems behaiour. Digital controllers, which act as reactive systems, can be very conveniently modeled with statecharts and efficiently synthesized in modern programmable devices. The paper presents in details syntax and semantics of statecharts and new implementation scheme. The issue of statecharts synthesis is not still ultimately solved. Main feature of the presented approach is the transformation of statechart diagrams into Finite State Machine, and through KISS format, functional decomposition and mapping into Embedded Memory Blocks. Embedded Memory are part of the modern programmable devices.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 1; 13-24
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Realizacja dekodera adresów z zastosowaniem w pełni określonych funkcji boolowskich
    Address Generator Realization Using Completely-Specified Boolean Functions
    Autorzy:
    Majchrzyk, M.
    Borowik, G.
    Darakchiev, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/156202.pdf
    Data publikacji:
    2008
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    synteza logiczna
    generator adresu
    układy sekwencyjne
    dekompozycja
    FPGA
    pamięci wbudowane
    komórka logiczna
    logic synthesis
    Address Generator
    finite state machine
    decomposition
    embedded memories
    logic cell
    Opis:
    Prezentujemy efektywną metodę syntezy w pełni określonych funkcji boolowskich charakteryzujących się dużą dysproporcją występującą na wyjściu. Opisywane funkcje zawierają jedynie mały podzbiór słów dla których wartość jest równa 1. Opracowano specjalny algorytm selekcji takich wektorów. Badania zostały wykonane na układach programowalnych FPGA Stratix firmy Altera. W porównaniu do klasycznych metod syntezy osiągnęliśmy, przy porównywalnym użyciu wbudowanych bloków pamięciowych EMB, redukcję zasobów logicznych LUT - średnio do 95%.
    We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today's FPGAs. In comparison with the classical logic synthesis methods we have obtained extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%. The investigation has been implemented using Altera's Stratix devices.
    Źródło:
    Pomiary Automatyka Kontrola; 2008, R. 54, nr 8, 8; 505-507
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Energy characteristic of a processor allocator and a network-on-chip
    Autorzy:
    Zydek, D.
    Selvaraj, H.
    Borowik, G.
    Łuba, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/907790.pdf
    Data publikacji:
    2011
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    wzmacniacz mocy
    model energetyczny
    przydział procesora
    CMP
    PA
    energy model
    processor allocation
    Opis:
    Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2011, 21, 2; 385-399
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-8 z 8

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