- Tytuł:
- Methodology for Implementing Scalable Run-Time Reconfigurable Devices
- Autorzy:
-
Kotynia, Ł.
Amrozik, P.
Napieralski, A. - Powiązania:
- https://bibliotekanauki.pl/articles/226469.pdf
- Data publikacji:
- 2011
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
design reuse
floorplanning
FPGA
implementation
verification
reconfigurable logic
timing analysis - Opis:
- The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.
- Źródło:
-
International Journal of Electronics and Telecommunications; 2011, 57, 2; 177-183
2300-1933 - Pojawia się w:
- International Journal of Electronics and Telecommunications
- Dostawca treści:
- Biblioteka Nauki
Artykuł