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    Wyświetlanie 1-9 z 9
    Tytuł:
    Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold
    Autorzy:
    Kalra, S.
    Bhattacharyya, A. B.
    Powiązania:
    https://bibliotekanauki.pl/articles/226500.pdf
    Data publikacji:
    2017
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    energy efficiency
    ultra-low power
    EKV
    minimum energy point
    minimum delay point temperature to time generator
    Opis:
    Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here.
    Źródło:
    International Journal of Electronics and Telecommunications; 2017, 63, 4; 369-374
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Ultra-low Power FinFET SRAM Cell with Improved Stability Suitable for Low Power Applications
    Autorzy:
    Birla, Shilpi
    Powiązania:
    https://bibliotekanauki.pl/articles/226772.pdf
    Data publikacji:
    2019
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    FinFET
    RSNM
    WSNM
    hold margin
    subthreshold
    leakage power
    Opis:
    In this paper, a new 11T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at sub-threshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV. At sub-threshold operation also it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Also, impact of process variation on cell stability is discussed.
    Źródło:
    International Journal of Electronics and Telecommunications; 2019, 65, 4; 603-609
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The Design Aspects for Ultra Low-Power, Low-Noise 90 nm CMOS Charge Sensitive Amplifier for the Active Pixel Detector
    Autorzy:
    Barzdenas, V.
    Navickas, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/1807954.pdf
    Data publikacji:
    2009-06
    Wydawca:
    Polska Akademia Nauk. Instytut Fizyki PAN
    Tematy:
    84.37.+q
    07.77.Ka
    Opis:
    A falling particle in the digital registration systems for elementary particles active pixel detector induces electric charge, the value of which describes the parameters of the particle in the detector. Since the electric charge induced by a single particle is relatively weak, the detector signal is first processed (amplified and shaped) right in the zone of irradiation and only then transmitted further. This paper analyses the primary analogical registration electronics for digital registration systems for elementary particles active pixel detectors, which is charge sensitive amplifiers operating in the nanoampere region.
    Źródło:
    Acta Physica Polonica A; 2009, 115, 6; 1139-1140
    0587-4246
    1898-794X
    Pojawia się w:
    Acta Physica Polonica A
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A 400 fJ per-cycle frequency reference for internet of things
    Autorzy:
    Coustans, M.
    Krummenacher, F.
    Terrier, C.
    Kayal, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/397716.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    time reference
    supply voltage insensitivity
    temperature insensitivity
    ultra-low power
    always on domain optimization
    odniesienie czasowe
    napięcie zasilające
    ultra low power
    Opis:
    This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted timekeeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultralow power operation in 0.18 μm CMOS technology; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/°C [-40°C - 60°C] and 0.07 %/V supply sensitivity.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 2; 41-46
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
    Autorzy:
    Smaani, Billel
    Meraihi, Yacin
    Nafa, Fares
    Benlatreche, Mohamed Salah
    Akroum, Hamza
    Latreche, Saida
    Powiązania:
    https://bibliotekanauki.pl/articles/2055208.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    double-gate MOSFET
    compact model
    ultra low power analog circuits
    Opis:
    This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 609--614
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Selected hardware solutions used in the process of monitoring bioparameters
    Autorzy:
    Michnik, A.
    Szczurek, Z.
    Szuster, B.
    Kubik, B.
    Kowalski, P.
    Powiązania:
    https://bibliotekanauki.pl/articles/397967.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    body area networks
    telemedicine
    ultra-low power
    inductive charging
    ECG
    GSR
    Bluetooth Low Energy
    BioSip
    sieć sensorowa na powierzchni ciała
    telemedycyna
    ultra low power
    ładowanie indukcyjne
    EKG
    Opis:
    The paper presents the idea behind the implementation of a system designed to monitor biomedical parameters and the subject's behaviour on the basis of the architecture of measurement modules located on the body. The system was developed as a result of market launch of new generations of electronic devices combining high functionality, small size and low power consumption. The paper presents the elements of the system called BioSip, along with hardware solutions selected for the objectives to be accomplished, i.e. providing communication between system elements that would be efficient and resistant to artefacts, extending the time of operation for battery power supply, as well as ensuring a satisfactory level of reliability and ease of use.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 1; 26-32
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation
    Autorzy:
    Wang, Y.
    Cai, H.
    Powiązania:
    https://bibliotekanauki.pl/articles/226202.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    cardiac pacemaker
    CMOS
    ultra-low power
    analogue-to-digital
    Sigma-Delta modulation
    continuous-time
    Opis:
    A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².
    Źródło:
    International Journal of Electronics and Telecommunications; 2014, 60, 1; 109-115
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Bezprzewodowa transmisja danych wizyjnych z wykorzystaniem ultra-energooszczędnego procesora msp430
    Wireless visual data transmission in system based on ultra-low power msp430 processor
    Autorzy:
    Andrzejewski, G.
    Zając, W.
    Górny, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/152582.pdf
    Data publikacji:
    2011
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    energooszczędny interaktywny system transmisji danych wizyjnych
    mikrokontroler MSP430
    moduł eZ430-RF2500T
    transmisja danych wizyjnych
    protokół SimpliciTI
    digital image transmission
    low-power interactive image transmission system
    MSP430
    eZ430-RF2500T
    SimpliciTI protocol
    Opis:
    Artykuł prezentuje wyniki prac nad realizacją energooszczędnego, interaktywnego systemu bezprzewodowej transmisji danych wizyjnych z wykorzystaniem układów radiowych ISM pracujących w paśmie 2,4GHz. Wykorzystano mikrokontrolery MSP430F2274 wchodzące w skład zestawu eZ430-RF2500T firmy Texas Instruments oraz moduły kamer C328R. Obsługę transmisji radiowej zapewnia układ radiowy CC2500. Założeniem projektowym było zapewnienie możliwości interaktywnej regulacji położenia kamery. System został zaprojektowany, zrealizowany i przebadany pod kątem zasięgu efektywnej transmisji, poboru mocy, odporności na zakłócenia oraz niezawodności transmisji.
    An important area of usage of wireless transmission are systems for secure, robust and energy-efficient visual data transmission. In the paper there are presented the results of work on a wireless digital visual data transmission interactive system, based on Texas Instruments RF communication modules eZ430-RF2500T. The modules operate in 2.4 GHz band and comprise MSP430F2274 microcontrollers and bi-directional RF communication modules CC2500. The system allows manipulating the camera direction with use of two micro-servos Turnigy TG9. In the paper the eZ430-RF2500T module is described [1, 4, 5, 6, 7, 11, 12] in Section 1, design conception and system components [2, 3, 7, 8] are discussed in Section 2, the system structure is presented in Section 3 (Fig. 1). Section 4 con-tains an overview of the research methodology applied [12, 13] and the results (Tables 1, 2, Figs. 2, 3, 4 and 5). There were measured four features of the system, namely: influence of interferences, energy efficiency, Multipatch Fading and Raleigh Fading. The interference testing included tests of influence of interferences generated by a microwave oven, Wi-Fi router and cell-phones. The power consumption tests included measurements in various system states of a transmitter and receiver. The multipath Fading tests were carried out in a sports hall divided into a mesh. Raleigh Fading research was realised in the same location, by transmitting a set of frames for an increasing distance. The results are discussed and summarised in Section 5.
    Źródło:
    Pomiary Automatyka Kontrola; 2011, R. 57, nr 9, 9; 989-992
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Advanced compact modeling of the deep submicron technologies
    Autorzy:
    Grabiński, W.
    Bucher, M.
    Sallese, J.-M.
    Krummenacher, F.
    Powiązania:
    https://bibliotekanauki.pl/articles/309312.pdf
    Data publikacji:
    2000
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    ultra deep submicron (UDSM) technology
    compact modeling
    EKV MOS transistor model
    MOSFET
    matching
    low power
    RF applications
    Opis:
    The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 žm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model
    Źródło:
    Journal of Telecommunications and Information Technology; 2000, 3-4; 31-42
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-9 z 9

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