- Tytuł:
- An efficient hardware implementation of a combinations generator
- Autorzy:
- Mazurkiewicz, T.
- Powiązania:
- https://bibliotekanauki.pl/articles/298447.pdf
- Data publikacji:
- 2017
- Wydawca:
- Uniwersytet Warmińsko-Mazurski w Olsztynie
- Tematy:
-
information technology
generator of combinations
field programmable gate array (FPGA) - Opis:
- In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.
- Źródło:
-
Technical Sciences / University of Warmia and Mazury in Olsztyn; 2017, 20(4); 405-413
1505-4675
2083-4527 - Pojawia się w:
- Technical Sciences / University of Warmia and Mazury in Olsztyn
- Dostawca treści:
- Biblioteka Nauki
Artykuł