Wszystkie pola: analog multipliers - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: An analog linear SVM image classifier
Autorzy:: Festila, L.
Szolga, L. A.
Groza, R.
Hintea, S.
Cirlugea, M.
Powiązania:: https://bibliotekanauki.pl/articles/385015.pdf
Data publikacji:: 2009
Wydawca:: Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
Tematy:: support vector machine (SVM)
analog multipliers
log-domain th domain
square-root domain
image classifier
Opis:: A linear Support Vector machine classifier is proposed in this paper. In such SVM architectures based on multiplying laws the main building blocks are multipliers. We propose in this paper multiplying and weighting cells, developed by using a model consisting of a compound of two inverse non-linear functions. This procedure is suitable for VLSI implementation because it permits the use of simple nonlinearized standard log-domain or DA cells that compensate each other nonlinearities to obtain an extended domain of operation. Current-mode ELIN (externally linear internally nonlinear) design is used for its low voltage, low power and high speed characteristics. The resulted parallel-serial classifier was simulated taking into account real parameters of transistors in BICMOS technology.
Źródło:: Journal of Automation Mobile Robotics and Intelligent Systems; 2009, 3, 2; 82-87
1897-8649
2080-2145
Pojawia się w:: Journal of Automation Mobile Robotics and Intelligent Systems
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters
Autorzy:: Machowski, W.
Kuta, S.
Jasielski, J.
Kołodziejski, W.
Powiązania:: https://bibliotekanauki.pl/articles/226683.pdf
Data publikacji:: 2010
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: analog VLSI
four-quadrant multiplier
CMOS circuits
low voltage circuits
Opis:: The paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.
Źródło:: International Journal of Electronics and Telecommunications; 2010, 56, 4; 381-386
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

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