Autor: Raskin, J. P. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: SOI Technology: An Opportunity for RF Designers?
Autorzy:: Raskin, J.-P.
Powiązania:: https://bibliotekanauki.pl/articles/308241.pdf
Data publikacji:: 2009
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: crosstalk
high resistivity silicon substrate
MOSFET
nonlinearities
silicon-on-insulator
wideband characterization
Opis:: This last decade silicon-on-insulator (SOI) MOS-FET technology has demonstrated its potentialities for high frequency (reaching cutoff frequencies close to 500 GHz for n-MOSFETs) and for harsh environments (high temperature, radiation) commercial applications. For RF and system-onchip applications, SOI also presents the major advantage of providing high resistivity substrate capabilities, leading to substantially reduced substrate losses. Substrate resistivity values higher than 1 k? cm can easily be achieved and high resistivity silicon (HRS) is commonly foreseen as a promising substrate for radio frequency integrated circuits (RFIC) and mixed signal applications. In this paper, based on several experimental and simulation results the interest, limitations but also possible future improvements of the SOI MOS technology are presented.
Źródło:: Journal of Telecommunications and Information Technology; 2009, 4; 3-17
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: On-wafer wideband characterization: a powerful tool for improving the IC technologies
Autorzy:: Lederer, D.
Raskin, J. P.
Powiązania:: https://bibliotekanauki.pl/articles/308775.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: silicon-on-insulator (SOI)
MOSFET
wideband characterization
microwave frequency
extraction techniques
small-signal equivalent circuit
Opis:: In the present paper, the interest of wideband characterization for the development of integrated technologies is highlighted through several advanced devices, such as 120 nm partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, 120 nm dynamic threshold (DT) voltage - SOI MOSFETs, 50 nm FinFETs as well as long-channel planar double gate (DG) MOSFETs.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 2; 69-77
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs
Autorzy:: Goffioul, M.
Vanhoenacker, D.
Raskin, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/309316.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
microwave devices
SOI MOSFET
Opis:: Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 59-66
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs
Autorzy:: Goffioul, M.
Dambrine, G.
Vanhoenacker, D.
Raskin, J.P.
Powiązania:: https://bibliotekanauki.pl/articles/309323.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: microelectronics
microwave devices
SOI MOSFET
Opis:: The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications.
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 72-80
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: The Impact of Externally Applied Mechanical Stress on Analog and RF Performances of SOI MOSFETs
Autorzy:: Emam, M.
Houri, S.
Vanhoenacker-Janvier, D.
Raskin, J.-P.
Powiązania:: https://bibliotekanauki.pl/articles/308245.pdf
Data publikacji:: 2009
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: cut-off frequency fT
intrinsic gain
mechanical stress
piezoresistance coefficient
SOI MOSFET
Opis:: This paper presents a complete study of the impact of mechanical stress on the performance of SOI MOSFETs. This investigation includes dc, analog and RF characteristics. Parameters of a small-signal equivalent circuit are also ex- tracted as a function of applied mechanical stress. Piezoresistance coefficientis shown to be a key element in describing the enhancement in the characteristics of the device due to mechanical stress.
Źródło:: Journal of Telecommunications and Information Technology; 2009, 4; 18-24
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 6.

Tytuł:: Impact of Crosstalk into High Resistivity Silicon Substrate on the RF Performance of SOI MOSFET
Autorzy:: Ali, K. B.
Neve, C. R.
Gharsallah, A.
Raskin, J. P.
Powiązania:: https://bibliotekanauki.pl/articles/308378.pdf
Data publikacji:: 2010
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: crosstalk
high resistivity Si
mixing products
passivation layer
polysilicon
Opis:: Crosstalk propagation through silicon substrate is a serious limiting factor on the performance of the RF devices and circuits. In this work, substrate crosstalk into high resistivity silicon substrate is experimentally analyzed and the impact on the RF behavior of silicon-on-insulator (SOI) MOS transistors is discussed. The injection of a 10 V peak-to-peak single tone noise signal at a frequency of 3 MHz ( fnoise) generates two sideband tones of ?56 dBm separated by fnoise from the RF output signal of a partially depleted SOI MOSFET at 1 GHz and 4.1 dBm. The efficiency of the introduction of a trap-rich polysilicon layer located underneath the buried oxide (BOX) of the high resistivity (HR) SOI wafer in the reduction of the sideband noise tones is demonstrated. An equivalent circuit to model and analyze the generation of these sideband noise tones is proposed.
Źródło:: Journal of Telecommunications and Information Technology; 2010, 4; 93-100
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 7.

Tytuł:: Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities
Autorzy:: Głuszko, G.
Łukasiak, L.
Kilchytska, V.
Chung, T. M.
Olbrechts, B.
Flandrie, D.
Raskin, J. P.
Powiązania:: https://bibliotekanauki.pl/articles/308669.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: charge-pumping
electrical characterization
interface traps
SOI
water bonding
Si layer transfer
Opis:: The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 3; 61-66
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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