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    Wyświetlanie 1-3 z 3
    Tytuł:
    The Implementation of the Parallel Scrambler Scheme for the IEEE 802.11 Standard
    Autorzy:
    Kudinov, A.
    Antimirov, Y.
    Tyshchenko, I.
    Popova, M.
    Cherepanov, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226358.pdf
    Data publikacji:
    2018
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    scrambler
    sequential circuit
    parallel circuit
    Opis:
    This article is devoted to the development of the scrambler circuit. Nowadays, new WiFi standard IEEE 802.11 is being put into operation, so that there is a huge need in modern, energy-efficient algorithms, which will be used in the data transmission. Consequently, some of the scrambler circuits, which could be implemented for the IEEE 802.11 standard are described with its comparison. In addition, an example in Python is given for readers to use it in their researches.
    Źródło:
    International Journal of Electronics and Telecommunications; 2018, 64, 1; 91-94
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Enhanced clock gating technique for power optimization in SRAM and sequential circuit
    Autorzy:
    Ashok Kumar, C.
    Madhavi, B.K.
    Lal Kishore, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/2141882.pdf
    Data publikacji:
    2021
    Wydawca:
    Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
    Tematy:
    enhanced clock gating
    D-Latch gating
    SRAM
    sequential circuit
    Area
    Delay
    Opis:
    Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.
    Źródło:
    Journal of Automation Mobile Robotics and Intelligent Systems; 2021, 15, 2; 32-38
    1897-8649
    2080-2145
    Pojawia się w:
    Journal of Automation Mobile Robotics and Intelligent Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding
    Autorzy:
    Bukowiec, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/227248.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    Boolean algebra
    circuit synthesis
    field programmable gate array (FPGA)
    sequential circuits
    Opis:
    The method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 1; 35-41
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-3 z 3

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