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    Wyświetlanie 1-4 z 4
    Tytuł:
    Hardware-efficient algorithms for implementation of the GHM discrete multiwavelet transform kernels
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114256.pdf
    Data publikacji:
    2016
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    multiwavelets
    GHM
    fast algorithms
    implementation complexity reduction
    FPGA implementation
    Opis:
    In this correspondence, we discuss two efficient algorithms for the execution of forward (FDMWT) and inverse (IDMWT) discrete multiwavelet transform basic operations with reduced computational complexities. We used multiwavelet basis proposed by Geronimo, Hadrin, and Massopust (GHM). The direct implementation of GHM-FDMWT basic operation requires 23 multiplications and 19 additions. The direct implementation of GHM-IDMWT basic operation requires 23 multiplication and 16 additions. At the same time, our solutions allow designing the computation procedures, which take only 10 multiplications plus 15 additions for GHM-FDMWT basic operation and 10 multiplications plus 10 additions for GHM-IDMWT basic operation
    Źródło:
    Measurement Automation Monitoring; 2016, 62, 6; 190-192
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Some Schemes for Implementation of Arithmetic Operations with Complex Numbers Using Squaring Units
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114347.pdf
    Data publikacji:
    2017
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    complex number arithmetic
    squaring unit
    implementation complexity reduction
    hardware implementation
    Opis:
    In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence of some number of general-purpose binary multipliers. The advantage of our solutions is a removing of multiplications through replacing them by less costly squarers. We use Logan's trick and quarter square technique, which propose to replace the calculation of the product of two real numbers by summing the squares. Replacing usual multipliers with digital squares implies the reducing power consumption as well as decreases the complexity of the hardware circuit. The squarer requiring less area and power as compared to general-purpose multiplier, it is interesting to assess the use of squarers to implementation of complex arithmetic.
    Źródło:
    Measurement Automation Monitoring; 2017, 63, 6; 209-211
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Hardware-Efficient Schemes of Quaternion Multiplying Units for 2D Discrete Quaternion Fourier Transform Processors
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Chicheva, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/114724.pdf
    Data publikacji:
    2017
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    discrete quaternion Fourier transform
    fast algorithms
    implementation complexity reduction
    FPGA implementation
    Opis:
    In this paper, we offer and discuss three efficient structural solutions for the hardware-oriented implementation of discrete quaternion Fourier transform basic operations with reduced implementation complexities. The first solution – a scheme for calculating sq product, the second solution – a scheme for calculating qt product, and the third solution – a scheme for calculating sqt product, where s is a so-called i -quaternion, t is an j - quaternion, and q – is an usual quaternion. The direct multiplication of two usual quaternions requires 16 real multiplications (or two-operand multipliers in the case of fully parallel hardware implementation) and 12 real additions (or binary adders). At the same time, our solutions allow to design the computation units, which consume only 6 multipliers plus 6 two input adders for implementation of sq or qt basic operations and 9 binary multipliers plus 6 two-input adders and 4 four-input adders for implementation of sqt basic operation.
    Źródło:
    Measurement Automation Monitoring; 2017, 63, 6; 206-208
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Hardware-Efficient Structure of the Accelerating Module for Implementation of Convolutional Neural Network Basic Operation
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114320.pdf
    Data publikacji:
    2018
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    convolution neural network
    Winograd’s minimal filtering
    algorithm
    implementation complexity reduction
    FPGA implementation
    Opis:
    This paper presents a structural design of the hardware-efficient module for implementation of convolution neural network (CNN) basic operation with reduced implementation complexity. For this purpose we utilize some modification of the Winograd’s minimal filtering method as well as computation vectorization principles. This module calculate inner products of two consecutive segments of the original data sequence, formed by a sliding window of length 3, with the elements of a filter impulse response. The fully parallel structure of the module for calculating these two inner products, based on the implementation of a naïve method of calculation, requires 6 binary multipliers and 4 binary adders. The use of the Winograd’s minimal filtering method allows to construct a module structure that requires only 4 binary multipliers and 8 binary adders. Since a high-performance convolutional neural network can contain tens or even hundreds of such modules, such a reduction can have a significant effect.
    Źródło:
    Measurement Automation Monitoring; 2018, 64, 2; 40-42
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-4 z 4

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