Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

Wyszukujesz frazę "complexity reduction" wg kryterium: Temat


Wyświetlanie 1-3 z 3
Tytuł:
An FPGA-oriented fully parallel algorithm for multiplying dual quaternions
Autorzy:
Cariow, A.
Cariowa, G.
Witczak, M.
Powiązania:
https://bibliotekanauki.pl/articles/114212.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
dual quaternion product
fast algorithms
hardware complexity reduction
FPGA
Opis:
This paper presents a low multiplicative complexity fully parallel algorithm for multiplying two dual quaternions. The “pen-and-paper” multiplication of two dual quaternions requires 64 real multiplications and 56 real additions. More effective solutions still do not exist. We show how to compute a product of two dual quaternions with 24 real multiplications and 64 real additions. During synthesis of the discussed algorithm we use the fact that the product of two dual quaternions can be represented as a matrix–vector product. The matrix multiplicand that participates in the product calculating has unique structural properties that allow performing its advantageous factorization. Namely this factorization leads to significant reducing of the multiplicative complexity of dual quaternion multiplication. We show that by using this approach, the computational process of calculating dual quaternion product can be structured so that eventually requires only half the number of multipliers compared to the direct implementation of matrix-vector multiplication.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 370-372
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Hardware-efficient algorithms for implementation of the GHM discrete multiwavelet transform kernels
Autorzy:
Cariow, A.
Cariowa, G.
Powiązania:
https://bibliotekanauki.pl/articles/114256.pdf
Data publikacji:
2016
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
multiwavelets
GHM
fast algorithms
implementation complexity reduction
FPGA implementation
Opis:
In this correspondence, we discuss two efficient algorithms for the execution of forward (FDMWT) and inverse (IDMWT) discrete multiwavelet transform basic operations with reduced computational complexities. We used multiwavelet basis proposed by Geronimo, Hadrin, and Massopust (GHM). The direct implementation of GHM-FDMWT basic operation requires 23 multiplications and 19 additions. The direct implementation of GHM-IDMWT basic operation requires 23 multiplication and 16 additions. At the same time, our solutions allow designing the computation procedures, which take only 10 multiplications plus 15 additions for GHM-FDMWT basic operation and 10 multiplications plus 10 additions for GHM-IDMWT basic operation
Źródło:
Measurement Automation Monitoring; 2016, 62, 6; 190-192
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Hardware-Efficient Schemes of Quaternion Multiplying Units for 2D Discrete Quaternion Fourier Transform Processors
Autorzy:
Cariow, A.
Cariowa, G.
Chicheva, M.
Powiązania:
https://bibliotekanauki.pl/articles/114724.pdf
Data publikacji:
2017
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
discrete quaternion Fourier transform
fast algorithms
implementation complexity reduction
FPGA implementation
Opis:
In this paper, we offer and discuss three efficient structural solutions for the hardware-oriented implementation of discrete quaternion Fourier transform basic operations with reduced implementation complexities. The first solution – a scheme for calculating sq product, the second solution – a scheme for calculating qt product, and the third solution – a scheme for calculating sqt product, where s is a so-called i -quaternion, t is an j - quaternion, and q – is an usual quaternion. The direct multiplication of two usual quaternions requires 16 real multiplications (or two-operand multipliers in the case of fully parallel hardware implementation) and 12 real additions (or binary adders). At the same time, our solutions allow to design the computation units, which consume only 6 multipliers plus 6 two input adders for implementation of sq or qt basic operations and 9 binary multipliers plus 6 two-input adders and 4 four-input adders for implementation of sqt basic operation.
Źródło:
Measurement Automation Monitoring; 2017, 63, 6; 206-208
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

    Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies