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Wyszukujesz frazę "digital signal processing." wg kryterium: Temat

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    Wyświetlanie 1-12 z 12
    Tytuł:
    Active power measurements - an overview and comparison of DSP algorithms by noncoherent sampling
    Autorzy:
    Sedlacek, M.
    Stoudek, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/220475.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    power estimation
    digital signal processing
    non-coherent sampling
    Opis:
    This paper presents an overview of algorithms for one-phase active power estimation using digital signal processing in the time domain and in the frequency domain, and compares the properties of these algorithms for a sinusoidal test signal. The comparison involves not only algorithms that have already been published, but also a new algorithm. Additional information concerning some known algorithms is also included. We present the results of computer simulations in MATLAB and measurement results gained by means of computer plug-in boards, both multiplexed and using simultaneous signal sampling. The use of new cosine windows with a recently published iterative algorithm is also included, and the influence of additive noise in the test signal is evaluated.
    Źródło:
    Metrology and Measurement Systems; 2011, 18, 2; 173-184
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Large Data Stream Processing : Embedded Systems Design Challenges
    Autorzy:
    Handzlik, A.
    Jabłonski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226898.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    reconfigurable hardware
    system on chip
    digital signal processing
    embedded systems
    Opis:
    The following paper describes an application of reconfigurable hardware architectures for processing of huge data streams. Radar, sonar and high speed internet networks are typical sources of data that require extreme computing power and resources to enable real time acquisition, processing and management. An approach to monitoring of real time multi-gigabit internet network has been described as a practical application of FPGA based board, designed for fast data processing.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 2; 107-110
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Direct Comparison of Analogue and Digital FGPA-Based Approaches to Synchronous Detection
    Autorzy:
    Teren, O.
    Tomlain, J.
    Sedlacek, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/221544.pdf
    Data publikacji:
    2018
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    synchronous detection
    lock-in amplifier
    digital signal processing
    FPGA
    measurement of impedance
    Opis:
    This paper deals with a comparison between digital and analogue implementation of a synchronous detection algorithm. The commonly used implementation methods of synchronous detection are presented in the paper. The paper describes FPGA-based digital and analogue hardware approaches, focusing on the digital design. The characteristics of used analogue-to-digital converters are measured. Both proposed approaches are directly compared in terms of sensitivity and long-term stability. The achieved results, along with identified limitations and proposed improvements are widely discussed.
    Źródło:
    Metrology and Measurement Systems; 2018, 25, 1; 57-69
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Digital Signal Processing Approach in Air Coupled Ultrasound Time Domain Beamforming
    Autorzy:
    Herman, K.
    Gudra, T.
    Furmankiewicz, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/177033.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    beamforming
    air-coupled ultrasounds
    DSP
    digital signal processing
    bat signals
    direction of arrival
    Opis:
    The work presents the results of experimental study on the possibilities of determining the source of an ultrasonic signal in two-dimensional space (distance, horizontal angle). During the research the team used a self-constructed linear array of MEMS microphones. Knowledge in the field of sonar systems was utilized to analyse and design a location system based on a microphone array. Using the above mentioned transducers and broadband ultrasound sources allows a quantitative comparison of estimation of the location of an ultrasonic wave source with the use of broadband modulated signals (modelled on bats’ echolocation signals) to be performed. During the laboratory research the team used various signal processing algorithms, which made it possible to select an optimal processing strategy, where the sending signal is known.
    Źródło:
    Archives of Acoustics; 2014, 39, 1; 37-50
    0137-5075
    Pojawia się w:
    Archives of Acoustics
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Research and Medical Transcranial Doppler System
    Autorzy:
    Lewandowski, M.
    Walczak, M.
    Karwat, P.
    Witek, B.
    Karłowicz, P.
    Powiązania:
    https://bibliotekanauki.pl/articles/177389.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    Doppler system
    digital signal processing
    hardware-software partitioning
    field programmable gate array (FPGA)
    Opis:
    A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a numer of spectrograms simultaneously and to reconstruct a flow velocity profile. The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost. The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.
    Źródło:
    Archives of Acoustics; 2016, 41, 4; 773-781
    0137-5075
    Pojawia się w:
    Archives of Acoustics
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    MULTI-EDIP - an intelligent software package for computer-aided multivariate signal and system identification
    Autorzy:
    Kasprzyk, J.
    Figwer, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/229907.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    computer-aided system identification
    parametric model identification
    nonparametric model identification
    digital signal processing
    Opis:
    In the paper an intelligent software package MULTI-EDIP for computer-aided identification of multivariate signals and systems is presented. Purposes and main requirements for computer-aided identification are discussed. A summary of the most important MULTI-EDIP services with a focus on expert advice is described. An example of using the package in electroacoustic plant identification for active noise control system development is presented.
    Źródło:
    Archives of Control Sciences; 2013, 23, 4; 427-446
    1230-2384
    Pojawia się w:
    Archives of Control Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Employing FPGA DSP blocks for time-to-digital conversion
    Autorzy:
    Kwiatkowski, Paweł
    Powiązania:
    https://bibliotekanauki.pl/articles/221505.pdf
    Data publikacji:
    2019
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    time-to-digital converter
    time coding line
    time interval counter
    digital signal processing
    field-programmable gate array
    Opis:
    The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.
    Źródło:
    Metrology and Measurement Systems; 2019, 26, 4; 631-643
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Construction of Generalized Rademacher Functions in Terms of Ternary Logic : Solving the Problem of Visibility of Using Galois Fields for Digital Signal Processing
    Autorzy:
    Vitulyova, Elizaveta S.
    Matrassulova, Dinara K.
    Suleimenov, Ibragim E.
    Powiązania:
    https://bibliotekanauki.pl/articles/2055235.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    digital signal processing
    non-binary Galois fields
    fourier transform
    rademacher functions
    walsh function
    multivalued logic
    visibility problem
    algebraic extensions
    ternary representation of number
    Opis:
    Generalized Rademacher functions, constructed as a sequence of elements of Galois fields are intended to find the spectral representation of signals with levels. These functions form a complete basis on the interval corresponding to -1 discrete time intervals and for passing into the classical Rademacher functions. The advantage of such spectra obtained using Galois Fields Fourier Transform is that the range of variation of the spectrum amplitudes remains the same as the range of variation of the original signal, which is modeled on discrete time functions taking values in the Galois field.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 2; 237--244
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Modified Block Sparse Bayesian Learning-Based Compressive Sensing Scheme For EEG Signals
    Autorzy:
    Upadhyaya, Vivek
    Salim, Mohammad
    Powiązania:
    https://bibliotekanauki.pl/articles/1844532.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    compressive sensing
    CS
    mean square error
    MSE
    structural similarity index measure
    SSIM
    electroencephalogram
    EEG
    digital signal processing
    DSP
    block sparse Bayesian learning
    BSBL
    Opis:
    Advancement in medical technology creates some issues related to data transmission as well as storage. In real-time processing, it is too tedious to limit the flow of data as it may reduce the meaningful information too. So, an efficient technique is required to compress the data. This problem arises in Magnetic Resonance Imaging (MRI), Electrocardiogram (ECG), Electroencephalogram (EEG), and other medical signal processing domains. In this paper, we demonstrate Block Sparse Bayesian Learning (BSBL) based compressive sensing technique on an Electroencephalogram (EEG) signal. The efficiency of the algorithm is described using the Mean Square Error (MSE) and Structural Similarity Index Measure (SSIM) value. Apart from this analysis we also use different combinations of sensing matrices too, to demonstrate the effect of sensing matrices on MSE and SSIM value. And here we got that the exponential and chi-square random matrices as a sensing matrix are showing a significant change in the value of MSE and SSIM. So, in real-time body sensor networks, this scheme will contribute a significant reduction in power requirement due to its data compression ability as well as it will reduce the cost and the size of the device used for real-time monitoring.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 3; 331-336
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Biometric speech signal processing in a system with digital signal processor
    Autorzy:
    Marciniak, T.
    Weychan, R.
    Stankiewicz, A.
    Dąbrowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/200794.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    biometry
    speech processing
    digital signal processor
    Gaussian mixture models
    vector quantization
    Opis:
    This paper presents an analysis of issues related to the fixed-point implementation of a speech signal applied to biometric purposes. For preparing the system for automatic speaker identification and for experimental tests we have used the Matlab computing environment and the development software for Texas Instruments digital signal processors, namely the Code Composer Studio (CCS). The tested speech signals have been processed with the TMS320C5515 processor. The paper examines limitations associated with operation of the realized embedded system, demonstrates advantages and disadvantages of the technique of automatic software conversion from Matlab to the CCS and shows the impact of the fixed-point representation on the speech identification effectiveness.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2014, 62, 3; 589-594
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Programmable, Asynchronous, Triangular Neighborhood Function for Self-Organizing Maps Realized on Transistor Level
    Autorzy:
    Kolasa, M.
    Długosz, R.
    Bieliński, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/226845.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    self-organizing maps
    parallel signal processing
    CMOS realization
    low energy consumption
    digital circuits
    Opis:
    A new hardware implementation of the triangular neighborhood function (TNF) for ultra-low power, Kohonen self-organizing maps (SOM) realized in the CMOS 0.18žm technology is presented. Simulations carried out by means of the software model of the SOM show that even low signal resolution at the output of the TNF block of 3-6 bits (depending on input data set) does not lead to significant disturbance of the learning process of the neural network. On the other hand, the signal resolution has a dominant influence on the overall circuit complexity i.e. the chip area and the energy consumption. The proposed neighborhood mechanism is very fast. For an example neighborhood range of 15 a delay between the first and the last neighboring neuron does not exceed 20 ns. This in practice means that the adaptation process starts in all neighboring neurons almost at the same time. As a result, data rates of 10-20 MHz are achievable, independently on the number of neurons in the map. The proposed SOM dissipates the power in-between 100 mW and 1 W, depending on the number of neurons in the map. For the comparison, the same network realized on PC achieves in simulations data rates in-between 10 Hz and 1 kHz. Data rate is in this case linearly dependend on the number of neurons.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 367-373
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine
    Autorzy:
    Mahendra, H. N.
    Mallikarjunaswamy, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/2134051.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    support vector machine
    SVM
    central processing unit
    CPU
    digital signal processor
    DSP
    field programmable gate array
    FPGA
    high level synthesis
    HLS
    hardware description language
    HDL
    Opis:
    This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 3; 609--617
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-12 z 12

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