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Wyszukujesz frazę "common mode" wg kryterium: Temat


Wyświetlanie 1-6 z 6
Tytuł:
An improved space vector modulation strategy for common-mode voltage reduction in matrix rectifier
Autorzy:
Liu, X.
Zhang, Q.
Hou, D.
Powiązania:
https://bibliotekanauki.pl/articles/950664.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
matrix converter
space vector modulation
common-mode voltage
Opis:
The matrix rectifier modulated by the classical space vector modulation (SVM) strategy generates common-mode voltage (CMV). The high magnitude and high du/dt of the CMV causes serious problems such as motor damage, electromagnetic noise and many others. In this paper, an improved SVM strategy is proposed by replacing the zero vectors with suitable couple of active ones that substantially eliminate the CMV. Theoretical analysis proves that the proposed strategy can reduce the amplitude of the CMV to half of the original value. In addition, the quality of the input and output waveforms is not affected by extra active vectors. Simulation and experimental results demonstrate the feasibility and effectiveness of the proposed strategy are shown.
Źródło:
Archives of Electrical Engineering; 2014, 63, 1; 93-106
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Common mode behavior in grid connected DC and AC decoupled PV Inverter topologies
Autorzy:
Sundar, D.J.
Kumaran, M.S.
Powiązania:
https://bibliotekanauki.pl/articles/141723.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
distributed generation
common mode leakage current
solar PV systems
transformerless PV inverters
Opis:
The transformer-less grid connected inverters are gaining more popularity due to their high efficiency, very low ground leakage current and economic feasibility especially in photovoltaic systems. The major issue which surfaces these systems is that of common mode leakage current which arises due to the absence of an electrical transformer connected between the inverter and the utility grid. Several topologies have evolved to reduce the impact of common mode leakage current and a majority of them have succeeded in eliminating the impacts and have well kept them within the limits of grid standards. This paper compares and analyses the impact of the common mode leakage current for four popular inverter configurations through simulation of the topologies such as H5, H6, HERIC and FBZVR inverters.
Źródło:
Archives of Electrical Engineering; 2016, 65, 3; 481-493
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Technique to improve CMRR at high frequencies in CMOS OTA-C filters
Autorzy:
Blakiewicz, G.
Powiązania:
https://bibliotekanauki.pl/articles/200504.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
common-mode rejection ratio
CMRR
CMOS
OTA
differential pair
OTA-C filters
component mismatch
Opis:
In this paper a technique to improve the common-mode rejection ratio (CMRR) at high frequencies in the OTA-C filters is proposed. The technique is applicable to most OTA-C filters using CMOS operational transconductance amplifiers (OTA) based on differential pairs. The presented analysis shows that a significant broadening of CMRR bandwidth can be achieved by using a differential pair with the bodies of transistors connected to AC ground, instead of using a pair with the bodies connected to the sources. The key advantages of the technique are: no increase in power consumption (except for an optional tuning circuit), a small increase of a chip area, a slight modification of the original filter. The simulation results for exemplary OTAs and a low-pass filter, designed in a 0.35 μm CMOS process, show the possibility of broadening the CMRR bandwidth several times.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2013, 61, 3; 697-703
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Differential and Common Mode Noise Waves and Correlation Matrices
Autorzy:
Dobrowolski, J. A.
Powiązania:
https://bibliotekanauki.pl/articles/226394.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
differential and common mode noise waves
mixed-mode noise wave correlation matrices
generalized multiport mixed-mode noise wave correlation matrice
Opis:
This paper presents an innovative extention of the noise wave definition to mixed mode, differential – and common-mode noise waves which can be used for noise analysis of differential microwave networks. Mixed mode noise waves are used next to define generalized mixed mode noise wave correlation matrices of microwave multiport networks. Presented approach may be used for noise analysis of microwave differential networks with differential ports as well as with conventional single ended ports.
Źródło:
International Journal of Electronics and Telecommunications; 2014, 60, 2; 133-141
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Resonant DC link inverters for AC motor drive systems – critical evaluation
Autorzy:
Turzyński, Marek
Chrzan, P. J.
Powiązania:
https://bibliotekanauki.pl/articles/200688.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
soft-switching
resonant DC link inverter
quasiresonant DC link inverter
common-mode voltage
voltage gradient
zero voltage switching
przekształtnik quasirezonansowy DC
gradient napięcia
przekształtnik rezonansowy DC/DC
Opis:
In this survey paper, resonant and quasiresonant DC link inverters are reexamined for AC motor drive applications. Critical evaluation of representative topologies is based on simulation and waveform analysis to characterize current/voltage stress of components, control timing constraints and feasibility. A special concern over inverter common-mode voltage and voltage gradient du/dt limitation capacity is discussed for motor bearing and winding insulation safety. Experimental records of the laboratory developed parallel quasiresonant DC link inverter feeding induction motor confirm results of analysis. Comparative tables and simulation results demonstrate characteristic features of various schemes.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2019, 67, 2; 241-252
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
Autorzy:
Khatak, Anil
Kumar, Manoj
Dhull, Sanjeev
Powiązania:
https://bibliotekanauki.pl/articles/1844527.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog to digital converter
ADC
successive approximation register (SAR)
common mode current feedback gain boosting
CMFD-GB
residue amplifier
RA
spurious free dynamic range
SFDR
integral nonlinearity
INL
differential nonlinearity
DNL
Opis:
A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-6 z 6

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