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Tytuł:
Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET
Autorzy:
Dargar, Abha
Srivastava, Viranjay M.
Powiązania:
https://bibliotekanauki.pl/articles/1844602.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
short-channel effects
metal oxide semiconductor
transistor
cylindrical surrounding double-gate
dual-material gate
microelectronics
nanotechnology
Opis:
In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 1; 29-34
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Realization of controlled NOT quantum gate via control of a two spin system
Autorzy:
Twardy, M.
Olszewski, D.
Powiązania:
https://bibliotekanauki.pl/articles/201766.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
quantum gates control
CNOT gate
quantum control
Opis:
Physical realization of controlled NOT quantum gate is addressed as a control problem for the system of two interacting spins. The control is carried out by magnetic pulses acting on the spins. The shapes of the appropriate magnetic pulses are computed.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2013, 61, 2; 379-390
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A current-source concept for fast and efficient driving of silicon carbide transistors
Autorzy:
Rąbkowski, J.
Powiązania:
https://bibliotekanauki.pl/articles/141047.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
silicon carbide transistors
gate drivers
current-source
switching process
Opis:
The paper discusses the application of the current-source concept in the gate drivers for silicon carbide transistors. There is a common expectation that all SiC devices will be switched very fast in order to reach very low values of switching energies. This may be achieved with the use of suitable gate drivers and one of possibilities is a solution with the current source. The basic idea is to store energy in magnetic field of a small inductor and then release it to generate the current peak of the gate current. The paper describes principles of the current-source driver as well as various aspects of practical implementation. Then, the switching performance of the driven SiC transistors is illustrated by double-pulse test results of the normally-ON and normally-OFF JFETs. Other issues such as problem of the drain-gate capacitance and power consumption are also discussed on the base of experimental results. All presented results show that the currentsource concept is an interesting option to fast and efficient driving of SiC transistors.
Źródło:
Archives of Electrical Engineering; 2013, 62, 2; 333-343
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
Autorzy:
Smaani, Billel
Meraihi, Yacin
Nafa, Fares
Benlatreche, Mohamed Salah
Akroum, Hamza
Latreche, Saida
Powiązania:
https://bibliotekanauki.pl/articles/2055208.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
double-gate MOSFET
compact model
ultra low power analog circuits
Opis:
This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 4; 609--614
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pulse Sequence Shaper For Radiospectroscopy And Relaxation Methods In NQR
Autorzy:
Bobalo, Y.
Hotra, Z.
Hotra, O.
Politans’kyy, L.
Samila, A.
Powiązania:
https://bibliotekanauki.pl/articles/221794.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
NQR
pulse sequence
field programmable gate array (FPGA)
frequency synthesizer
Opis:
A pulse sequence shaper for the pursuance of the research using a wide spectrum of radiospectroscopy and relaxation methods in NQR is proposed. The distinctive feature of this product is its implementation with the application of a multi-functional programmable frequency synthesizer suitable for high-speed amplitude and phase manipulations.
Źródło:
Metrology and Measurement Systems; 2015, 22, 3; 363-370
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The Algorithm for Reversible Circuits Synthesis
Autorzy:
Skorupski, Andrzej
Gracki, Krzysztof
Powiązania:
https://bibliotekanauki.pl/articles/226226.pdf
Data publikacji:
2020
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
reversible logic
reversible circuits
reversible gate
CNT set of the gates
Opis:
In this paper the new synthesis method for reversible networks is proposed. The method is suitable to generate optimal circuits. The examples will be shown for three variables reversible functions but the method is scalable to larger number of variables. The algorithm could be easily implemented with high speed execution and without big consuming storage software. Section 1 contains general concepts about the reversible functions. In Section 2 there are presented various descriptions of reversible functions. One of them is the description using partitions. In Section 3 there are introduced the cascade of the reversible gates as the target of the synthesis algorithm. In order to achieve this target the definitions of the rest and remain functions will be helpful. Section 4 contains the proposed algorithm. There is introduced a classification of minterms distribution for a given function. To select the successive gates in the cascade the condition of the improvement the minterms distribution must be fulfilled. Section 4 describes the algorithm how to improve the minterms distributions in order to find the optimal cascade. Section 5 shows the one example of this algorithm.
Źródło:
International Journal of Electronics and Telecommunications; 2020, 66, 2; 281-286
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The Transforming Method Between Two Reversible Functions
Autorzy:
Skorupski, Andrzej
Gracki, Krzysztof
Powiązania:
https://bibliotekanauki.pl/articles/226430.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
reversible logic
reversible circuits
reversible gate
CNT set of the gates
Opis:
This paper presents an original method of designing some special reversible circuits. This method is intended for the most popular gate set with three types of gates CNT (Control, NOT and Toffoli). The presented algorithm is based on two types of cascades with these reversible gates. The problem of transformation between two reversible functions is solved. This method allows to find optimal reversible circuits. The paper is organized as follows. Section 1 and 2 recalls basic concepts of reversible logic. Especially the two types of cascades of reversible function are presented. In Section 3 there is introduced a problem of analysis of the cascades. Section 4 describes the method of synthesis of the optimal cascade for transformation of the given reversible function into another one.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 1; 33-38
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding
Autorzy:
Bukowiec, A.
Powiązania:
https://bibliotekanauki.pl/articles/227248.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
Boolean algebra
circuit synthesis
field programmable gate array (FPGA)
sequential circuits
Opis:
The method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 1; 35-41
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing
Autorzy:
Łoza, S.
Matuszewski, Ł.
Jessa, M.
Powiązania:
https://bibliotekanauki.pl/articles/963943.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
random numbers
cryptography
ring oscillators
hash functions
field programmable gate array (FPGA)
Opis:
Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.
Źródło:
International Journal of Electronics and Telecommunications; 2015, 61, 2; 199-204
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Research and Medical Transcranial Doppler System
Autorzy:
Lewandowski, M.
Walczak, M.
Karwat, P.
Witek, B.
Karłowicz, P.
Powiązania:
https://bibliotekanauki.pl/articles/177389.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
Doppler system
digital signal processing
hardware-software partitioning
field programmable gate array (FPGA)
Opis:
A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a numer of spectrograms simultaneously and to reconstruct a flow velocity profile. The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost. The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.
Źródło:
Archives of Acoustics; 2016, 41, 4; 773-781
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Evaluation of gate drive circuit effect in cascode GaN-based applications
Autorzy:
Tan, Q. Y.
Narayanan, E. M. S.
Powiązania:
https://bibliotekanauki.pl/articles/2173545.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
cascode GaNFETs
parasitics
buck converter
gate drive design
kaskoda GaNFETs
przetwornica
pasożytnictwo
projekt napędu bramy
Opis:
This work evaluates the influence of gate drive circuitry to cascode GaN device’s switching waveforms. This is done by comparing three PCBs using three double-pulse-test (DPT) with different gate driving loop design. Among important parasitic elements, source-side inductance shows a significant impact to gate-source voltage waveform. A simulation model based on experimental measurement of the cascode GaNFET used in this work is modified by author. The simulation model is implemented in a synchronous buck converter topology and hereby to assess the impact of gate driving loop of cascode GaN device in both continuous conduction mode (CCM) and critical conduction mode (CRM). Apart from simulation, a synchronous buck converter prototype is presented for experimental evaluation, which shows a 99.15% efficiency at 5A under soft-switching operation (CRM) with a 59ns dead-time.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; art. no. e136742
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Evaluation of gate drive circuit effect in cascode GaN-based applications
Autorzy:
Tan, Q. Y.
Narayanan, E. M. S.
Powiązania:
https://bibliotekanauki.pl/articles/2128152.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
cascode GaNFETs
parasitics
buck converter
gate drive design
kaskoda GaNFETs
przetwornica
pasożytnictwo
projekt napędu bramy
Opis:
This work evaluates the influence of gate drive circuitry to cascode GaN device’s switching waveforms. This is done by comparing three PCBs using three double-pulse-test (DPT) with different gate driving loop design. Among important parasitic elements, source-side inductance shows a significant impact to gate-source voltage waveform. A simulation model based on experimental measurement of the cascode GaNFET used in this work is modified by author. The simulation model is implemented in a synchronous buck converter topology and hereby to assess the impact of gate driving loop of cascode GaN device in both continuous conduction mode (CCM) and critical conduction mode (CRM). Apart from simulation, a synchronous buck converter prototype is presented for experimental evaluation, which shows a 99.15% efficiency at 5A under soft-switching operation (CRM) with a 59ns dead-time.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; e136742, 1--7
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Compact nanosecond pulse generator based on IGBT and spark gap cooperation
Autorzy:
Achour, Y.
Starzyński, J.
Łasica, A.
Powiązania:
https://bibliotekanauki.pl/articles/202157.pdf
Data publikacji:
2020
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
pulsed power
nanosecond generator
Isolated Gate Bipolar Transistor (IGBT)
spark gap
avalanche mode Bipolar Junction Transistor
Opis:
The present paper describes a new architecture of a high-voltage solid-state pulse generator. This generator combines the two types of energy storage systems: inductive and capacitive, and consequently operates two types of switches: opening and closing. For the opening switch, an isolated gate bipolar transistor (IGBT) was chosen due to its interesting characteristics in terms of controllability and robustness. For the closing switch, two solutions were tested: spark-gap (SG) for a powerful low-cost solution and avalanche mode bipolar junction transistor (BJT) for a fully semiconductor structure. The new architecture has several advantages: simple structure and driving system, high and stable controllable repetition rate that can reach 1 kHz, short rising time of a few nanoseconds, high gain and efficiency, and low cost. The paper starts with the mathematical analysis of the generator operation followed by numerical simulation of the device. Finally add a comma the results were confirmed by the experimental test with a prototype generator. Additionally, a comparative study was carried out for the classical SG versus the avalanche mode BJT working as a closing switch.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2020, 68, 2; 377-388
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Employing FPGA DSP blocks for time-to-digital conversion
Autorzy:
Kwiatkowski, Paweł
Powiązania:
https://bibliotekanauki.pl/articles/221505.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
time-to-digital converter
time coding line
time interval counter
digital signal processing
field-programmable gate array
Opis:
The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.
Źródło:
Metrology and Measurement Systems; 2019, 26, 4; 631-643
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
FPGA implementation of DPWM utility/DG interfaced solar (PV) power converter for green home power supply
Autorzy:
Singh, S. N.
Mishra, S.
Powiązania:
https://bibliotekanauki.pl/articles/229942.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
direct pulse width modulation (DPWM)
total harmonic distortion THD
field SMF: sealed maintenance
free programmable gate array (FPGA)
Opis:
In this paper, utility/DG interfaced DPWM solar (PV) power converter (SPC) has been proposed and developed to meet the growing green energy demand of household applications in a developing country like India. The use of new software based direct PWM strategy (DPWM) in the inverter circuit has resulted in to produce a very near sine-wave, most suitable for various home loads. Simulated results of proposed PWM output wave form and computation of its harmonics content in terms of THD value (upto 5% or even less) using MATLAB software has been reflected in the proposed scheme. The features like an intelligent control action to prevent battery from overcharge or undercharge, higher efficiency (> 90%), generation of grid quality green electricity, sustainability of solar renewable energy sources, cost effective hardware realization with FPGA based VLSI embedded system, shows the superiority of the proposed scheme over conventional power supply systems.
Źródło:
Archives of Control Sciences; 2011, 21, 4; 461-469
1230-2384
Pojawia się w:
Archives of Control Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 25

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