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Wyświetlanie 1-10 z 10
Tytuł:
Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs
Autorzy:
Abdollahvand, S.
Goes, J.
Paulino, N.
Gomes, L.
Powiązania:
https://bibliotekanauki.pl/articles/397961.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
filtr decymacyjny
filtr wielofazowy
modulator sigma-delta
field-programmable gate array
FPGA
decimation filter
Polyphase Comb filter
sigma-delta modulators
field programmable gate array (FPGA)
Opis:
This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 4; 152-158
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
FPGA implementations of low precision floating point multiply-accumulate
Autorzy:
Amaricai, A.
Boncalo, O.
Sicoe, O
Powiązania:
https://bibliotekanauki.pl/articles/397897.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
digital arithmetic
floating point arithmetic
FPGA
field programmable gate array (FPGA)
multiply-accumulate
dot product
arytmetyka cyfrowa
arytmetyka zmiennoprzecinkowa
field-programmable gate array
MAC
iloczyn skalarny
Opis:
Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 4; 159-163
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Calibration of a mixed-signal power network transient stability analysis emulator
Autorzy:
Lanz, G
Fabre, L.
Lilis, G
Kyriakidis, T
Sallin, D
Cherkaoui, R.
Kayal, M.
Powiązania:
https://bibliotekanauki.pl/articles/398094.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
analog computer
calibration
field programmable gate array (FPGA)
FPGA
mixed signal
power system dynamics
komputer analogowy
kalibracja
field-programmable gate array
sygnał mieszany
dynamika systemu elektroenergetycznego
Opis:
The emerging field of power system emulation for real time smart grid management is very demanding in terms of speed and accuracy. This paper provides detailed information about the electronics calibration process of a high-speed power network emulator dedicated to the transient stability analysis of power systems. This emulator uses mixed-signal hardware to model the dynamic behavior of a power network. Special design allows the self-calibration of the analog electronics through successive measurements and correction steps. The calibration operation guarantees high resolution of the transient stability analysis results, so that they can be reliably used for operational planning and control on real power networks.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 4; 142-147
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Small-Signal Parameters of the VeSFET and Its Application in Analog Circuits
Autorzy:
Kasprowicz, D.
Swacha, B
Powiązania:
https://bibliotekanauki.pl/articles/397889.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
VeSFET
VeSTIC
OTA
układ analogowy
analog circuit
dual-gate device
independent gates
Opis:
The Vertical Slit-based Field-Effect Transistor (VeSFET) is a novel junctionless device with two identical, independently controlled gates. The VeSFET, so far prototyped only as single-device test structures, has been considered in the literature exclusively as a component of digital systems. This article shows that the device’s properties make it attractive also for the analog designer. Some of the VeSFET’s analog-design related parameters are compared with those of the MOSFET of the corresponding technology node. Subsequently, a two-stage Miller operational transconductance amplifier (OTA) is proposed that makes use of the VeSFET’s two independently-controlled gates to drastically reduce the common-mode gain. An example application of the OTA in a current mirror is also presented.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 2; 79-86
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Area equivalent WKB Compact modeling approach for tunneling probability in Hetero-Junction TFETs including ambipolar behaviour
Autorzy:
Horst, Fabian
Farokhnejad, Atieh
Darbandy, Ghader
Iñíguez, Benjamín
Kloes, Alexander
Powiązania:
https://bibliotekanauki.pl/articles/397787.pdf
Data publikacji:
2018
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
TFET
tunneling probability
WKB approximation
heterojunction
compact modeling
closed-form
double-gate
DG
ambipolarity
modelowanie kompaktowe
dwubiegunowość
Opis:
This paper introduces an innovative modeling approach for calculating the band-to-band (B2B) tunneling probability in tunnel-field effect transistors (TFETs). The field of application is the usage in TFET compact models. Looking at a tunneling process in TFETs, carriers try to tunnel through an energy barrier which is defined by the device band diagram. The tunneling energy barrier is approximated by an approach which assumes an area equivalent (AE) triangular shaped energy profile. The simplified energy triangle is suitable to be used in the Wentzel-Kramers-Brillouin (WKB) approximation. Referring to the area instead of the electric field at individual points is shown to be a more robust approach in terms of numerical stability. The derived AE approach is implemented in an existing compact model for double-gate (DG) TFETs. In order to verify and show the numerical stability of this approach, modeling results are compared to TCAD Sentaurus simulation data for various sets of device parameters, whereby the simulations include both ON- and AMBIPOLAR-state of the TFET. In addition to the various device dimensions, the source material is also changed to demonstrate the feasibility of simulating hetero-junctions. Comparing the modeling approach with TCAD data shows a good match. Apart the limitations demonstrated and discussed in this paper, the main advantage of the AE approach is the simplicity and a better fit to TCAD data in comparison to the quasi-2D WKB approach.
Źródło:
International Journal of Microelectronics and Computer Science; 2018, 9, 2; 47-59
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Reduced stress and fluctuation for the integrated α-Si TFT gate driver on the LCD
Autorzy:
Huang, N. X.
Shiau, M. S.
Wu, H.-C.
Sun, R. C.
Liu, D.-G.
Powiązania:
https://bibliotekanauki.pl/articles/397883.pdf
Data publikacji:
2010
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
sterownik bramy
fluktuacja hałasu
wpływ naprężenia
system w panelu
gate driver
fluctuation noise
stress effect
system on panel (SoP)
Opis:
In this paper, an integrated TFT gate driver was designed on the glass substrate not only to decrease the fluctuation at the output, but also to reduce the stress effect on the pull-down branches. The fluctuation in the voltage at the output transistor was attributed to the coupled clocks through the parasitic capacitors in the TFTs. In this study, the voltage gating the pull-down braches was reduced for longer operational lifetime. This scheme was investigated by simulation by Smart-SPICE with an α-Si TFT model from Wintek Inc. at level 35.
Źródło:
International Journal of Microelectronics and Computer Science; 2010, 1, 3; 311-315
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Surface Potential Modeling of a High-k HfO2-Ta2O5 Capacitor in Verilog-A
Autorzy:
Angelov, G. V.
Powiązania:
https://bibliotekanauki.pl/articles/397997.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
modelowanie elementów elektronicznych
model kompaktowy
PSP
symulacja obwodu
dielektryk bramkowy o wysokiej przenikalności elektrycznej
Verilog-A
Spectre
device modeling
compact models
circuit simulation
high-k gate dielectric
Opis:
A compact model of a high-k HfO2-Ta2O5 mixed layer capacitor stack is developed in Matlab. Model equations are based on the surface potential PSP model. After fitting the C-V characteristics in Matlab the model is coded in Verilog-A hardware description language and it is implemented as external library in Spectre circuit simulator within Cadence CAD system. The results are validated against the experimental measurements of the HfO2-Ta2O5 stack structure.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 3; 111-118
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Modeling the characteristics of high-k HfO2-Ta2O5 capacitor in Verilog-A
Autorzy:
Angelov, G. V.
Powiązania:
https://bibliotekanauki.pl/articles/398142.pdf
Data publikacji:
2011
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
modelowanie elementów elektronicznych
model kompaktowy
symulacja obwodu
dielektryk bramkowy o wysokiej przenikalności elektrycznej
Verilog-A
Spectre
device modeling
compact models
circuit simulation
high-k gate dielectric
Opis:
A circuit simulation model of a MOS capacitor with high-k HfO2-Ta2O5 mixed layer is developed and coded in Verilog-A hardware description language. Model equations are based on the BSIM3v3 model core. Capacitance-voltage (C-V) and current-voltage (I-V) characteristics are simulated in Spectre circuit simulator within Cadence CAD system and validated against experimental measurements of the HfO2-Ta2O5 slack structure.
Źródło:
International Journal of Microelectronics and Computer Science; 2011, 2, 3; 105-112
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Rapid NEGF-based calculation of ballistic current in ultra-short DG MOSFETs for circuit simulation
Autorzy:
Hosenfeld, F.
Horst, F..
Graef, M.
Farokhnejad, A.
Kloes, A.
Iniguez, B.
Lime, F.
Powiązania:
https://bibliotekanauki.pl/articles/397995.pdf
Data publikacji:
2016
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
ultra-short Double-Gate MOSFET
nonequilibrium Green's function
NEGF
ballistic transport
source-to-drain tunneling
ultra-thin body
UTB
compact model
multi-scale simulation
nierównowagowe funkcje Greena
transport balistyczny
tunelowanie źródło-dren
model kompaktowy
symulacja wieloskalowa
Opis:
Shrinking gate length in conventional MOSFETs leads to increasing short channel effects like source-to-drain (SD) tunneling. Compact modeling designers are challenged to model these quantum mechanical effects. The complexity lies in the set-up between time efficiency, physical model relation and analytical equations. Multi-scale simulation bridges the gap between compact models, its fast and efficient calculation of the device terminal voltages, and numerical device models which consider the effects of nanoscale devices. These numerical models iterate between Poisson- and Schroedinger equation which significantly slows down the simulation performance. The physicsbased consideration of quantum effects like the SD tunneling makes the non-equilibrium Green’s function (NEGF) to a stateof-the-art method for the simulation of devices in the sub 10 nm region. This work introduces a semi-analytical NEGF model for ultra-short DG MOSFETs. Applying the closed-form potential solution of a classical compact model, the model turns the NEGF from an iterative numerical solution into a straightforward calculation. The applied mathematical approximations speed up the calculation time of the 1D NEGF. The model results for the ballistic channel current in DG-MOSFETs are compared with numerical NanoMOS TCAD [1] simulation data. Shown is the accurate potential calculation as well as the good agreement of the current characteristic for temperatures down to 75 K for channel lengths from 6 nm to 20 nm and channel thickness from 1.5 nm to 3 nm.
Źródło:
International Journal of Microelectronics and Computer Science; 2016, 7, 2; 65-72
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Simulation framework and thorough analysis of the impact of barrier lowering on the current in SB-MOSFETs
Autorzy:
Schwarz, M.
Calvet, L. E.
Snyde, J. P.
Krauss, T.
Schwalke, U.
Kloes, A.
Powiązania:
https://bibliotekanauki.pl/articles/397793.pdf
Data publikacji:
2017
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
2D Poisson equation
device modeling
double-gate MOSFET
field emission
framework
Schottky barrier
Synopsys
TCAD
thermionic emission
thermionic current
tunneling current
dwuwymiarowe równanie Poissona
modelowanie elementów elektronicznych
dwubramkowy tranzystor MOS
emisja polowa
bariera Schottky'ego
emisja termoelektronowa
prąd termoelektronowy
prąd tunelowy
Opis:
In this paper we present a simulation framework to account for the Schottky barrier lowering models in SBMOSFETs within the Synopsys TCAD Sentaurus tool-chain. The improved Schottky barrier lowering model for field emission is considered. A strategy to extract the different current components and thus accurately predict the on- and off-current regions are adressed. Detailed investigations of these components are presented along with an improved Schottky barrier lowering model for field emission. Finally, a comparison for the transfer characteristics is shown for simulation and experimental data.
Źródło:
International Journal of Microelectronics and Computer Science; 2017, 8, 2; 72-79
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-10 z 10

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