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    Wyświetlanie 1-4 z 4
    Tytuł:
    A Hardware-Efficient Structure of Complex Numbers Divider
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114589.pdf
    Data publikacji:
    2017
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    complex-number divider
    hardware complexity reduction
    VLSI implementation
    Opis:
    In this correspondence an efficient approach to structure of hardware accelerator for calculating the quotient of two complex-numbers with reduced number of underlying binary multipliers is presented. The fully parallel implementation of a complex-number division using the conventional approach to structure organization requires 4 multipliers, 3 adders, 2 squarers and 2 divider while the proposed structure requires only 3 multipliers, 6 adders, 2 squarers and 2 divider. Because the hardware complexity of a binary multiplier grows quadratically with operand size, and the hardware complexity of an binary adder increases linearly with operand size, then the complex-number divider structure containing as little as possible embedded multipliers is preferable.
    Źródło:
    Measurement Automation Monitoring; 2017, 63, 6; 212-213
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An FPGA-oriented fully parallel algorithm for multiplying dual quaternions
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Witczak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/114212.pdf
    Data publikacji:
    2015
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    dual quaternion product
    fast algorithms
    hardware complexity reduction
    FPGA
    Opis:
    This paper presents a low multiplicative complexity fully parallel algorithm for multiplying two dual quaternions. The “pen-and-paper” multiplication of two dual quaternions requires 64 real multiplications and 56 real additions. More effective solutions still do not exist. We show how to compute a product of two dual quaternions with 24 real multiplications and 64 real additions. During synthesis of the discussed algorithm we use the fact that the product of two dual quaternions can be represented as a matrix–vector product. The matrix multiplicand that participates in the product calculating has unique structural properties that allow performing its advantageous factorization. Namely this factorization leads to significant reducing of the multiplicative complexity of dual quaternion multiplication. We show that by using this approach, the computational process of calculating dual quaternion product can be structured so that eventually requires only half the number of multipliers compared to the direct implementation of matrix-vector multiplication.
    Źródło:
    Measurement Automation Monitoring; 2015, 61, 7; 370-372
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Some Schemes for Implementation of Arithmetic Operations with Complex Numbers Using Squaring Units
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114347.pdf
    Data publikacji:
    2017
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    complex number arithmetic
    squaring unit
    implementation complexity reduction
    hardware implementation
    Opis:
    In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence of some number of general-purpose binary multipliers. The advantage of our solutions is a removing of multiplications through replacing them by less costly squarers. We use Logan's trick and quarter square technique, which propose to replace the calculation of the product of two real numbers by summing the squares. Replacing usual multipliers with digital squares implies the reducing power consumption as well as decreases the complexity of the hardware circuit. The squarer requiring less area and power as compared to general-purpose multiplier, it is interesting to assess the use of squarers to implementation of complex arithmetic.
    Źródło:
    Measurement Automation Monitoring; 2017, 63, 6; 209-211
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Basic Aspects of Designing a High-performance Processor Structure for Calculating a "true" Discrete Fractional Fourier Transform
    Autorzy:
    Cariow, A.
    Majorkowska-Mech, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/114579.pdf
    Data publikacji:
    2018
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    discrete fractional Fourier transform
    parallelization of computations
    hardware implementation
    complexity reduction
    Opis:
    This paper presents a basic aspects of structural design of the highperformance processor for implementation of discrete fractional Fourier transform (DFrFT). The general idea of the possibility of parallelizing the calculation of the so-called “true” discrete Fourier transform on the basis of our previously developed algorithmic approach is presented. We specifically focused only on the general aspects of the organization of the structure of such a processor, since the details of a particular implementation always depend on the implementation platform used, while the general idea of constructing the structure of the processor remains unchanged.
    Źródło:
    Measurement Automation Monitoring; 2018, 64, 2; 43-45
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-4 z 4

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