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    Wyświetlanie 1-11 z 11
    Tytuł:
    Hardware implementation of a decision tree classifier for object recognition applications
    Autorzy:
    Fularz, M.
    Kraft, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/114595.pdf
    Data publikacji:
    2015
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    decision tree
    hardware implementation
    FPGA
    object recognition
    Opis:
    Hardware implementation of a widely used decision tree classifier is presented in this paper. The classifier task is to perform image-based object classification. The performance evaluation of the implemented architecture in terms of resource utilization and processing speed are reported. The presented architecture is compact, flexible and highly scalable and compares favorably to software-only solutions in terms of processing speed and power consumption.
    Źródło:
    Measurement Automation Monitoring; 2015, 61, 7; 379-381
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Synchronous and asynchronous structural implementation of Łukasiewicz norms in Spartan-6 FPGAs
    Autorzy:
    Surdej, Ł.
    Gniewek, L.
    Powiązania:
    https://bibliotekanauki.pl/articles/114322.pdf
    Data publikacji:
    2016
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    fuzzy hardware
    fuzzy Łukasiewicz norms
    FPGA
    Opis:
    Fast time to market, high performance and low cost make new FPGAs a competition for dedicated VLSI device in many area. Their array architecture with lots of programmable resources and IO pins is attractive hardware platform for implementation a complex fuzzy systems. The article discusses the realization of fuzzy Łukasiewicz operations in Xilinx Spartan6 FPGAs, which in addition to Zadeh operations, are basic elements in fuzzy systems. Safe behavioral description of these operations that define functionalities independent of the hardware platform are presented. Structural descriptions of both synchronous and asynchronous fuzzy operations are shown, to carry out their primitive level realization and the effective utilization of basic elements of the FPGA structure. As the result the area optimized implementation of Łukasiewicz operations are obtained.
    Źródło:
    Measurement Automation Monitoring; 2016, 62, 11; 361-366
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An FPGA-oriented fully parallel algorithm for multiplying dual quaternions
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Witczak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/114212.pdf
    Data publikacji:
    2015
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    dual quaternion product
    fast algorithms
    hardware complexity reduction
    FPGA
    Opis:
    This paper presents a low multiplicative complexity fully parallel algorithm for multiplying two dual quaternions. The “pen-and-paper” multiplication of two dual quaternions requires 64 real multiplications and 56 real additions. More effective solutions still do not exist. We show how to compute a product of two dual quaternions with 24 real multiplications and 64 real additions. During synthesis of the discussed algorithm we use the fact that the product of two dual quaternions can be represented as a matrix–vector product. The matrix multiplicand that participates in the product calculating has unique structural properties that allow performing its advantageous factorization. Namely this factorization leads to significant reducing of the multiplicative complexity of dual quaternion multiplication. We show that by using this approach, the computational process of calculating dual quaternion product can be structured so that eventually requires only half the number of multipliers compared to the direct implementation of matrix-vector multiplication.
    Źródło:
    Measurement Automation Monitoring; 2015, 61, 7; 370-372
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A Hardware-Efficient Structure of Complex Numbers Divider
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114589.pdf
    Data publikacji:
    2017
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    complex-number divider
    hardware complexity reduction
    VLSI implementation
    Opis:
    In this correspondence an efficient approach to structure of hardware accelerator for calculating the quotient of two complex-numbers with reduced number of underlying binary multipliers is presented. The fully parallel implementation of a complex-number division using the conventional approach to structure organization requires 4 multipliers, 3 adders, 2 squarers and 2 divider while the proposed structure requires only 3 multipliers, 6 adders, 2 squarers and 2 divider. Because the hardware complexity of a binary multiplier grows quadratically with operand size, and the hardware complexity of an binary adder increases linearly with operand size, then the complex-number divider structure containing as little as possible embedded multipliers is preferable.
    Źródło:
    Measurement Automation Monitoring; 2017, 63, 6; 212-213
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The versatile hardware accelerator framework for sparse vector calculations
    Autorzy:
    Karwatowski, R.
    Wiatr, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/114705.pdf
    Data publikacji:
    2015
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    FPGA
    sparse vectors
    cosine similarity
    Zynq
    hardware accelerator
    Opis:
    In this paper, we present the advantage of the ability of FPGAs to perform various computationally complex calculations using deep pipelining and parallelism. We propose an architecture that consists of many small stream processing blocks. The designed framework maintains proper data movement and synchronization. The architecture can be easily adapted to be implemented in FPGA devices of a various size and cost - from small SoC devices to high-end PCIe accelerator cards. It is capable to perform a selected operation on a sparse data that are loaded as the stream of vectors. As an example application, we have implemented the cosine similarity measure for the text similarity calculations that uses the TF-IDF weighting scheme. The presented example application calculates the similarity of texts from the set of input documents to documents from the large database. The scheme is used to find the most similar documents. The proposed design can decrease the service time of search queries in computer centers while reducing power consumption.
    Źródło:
    Measurement Automation Monitoring; 2015, 61, 7; 327-329
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Simple distributed system hardware platform for basic research
    Autorzy:
    Krzywicki, K.
    Andrzejewski, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114714.pdf
    Data publikacji:
    2015
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    distributed systems
    embedded systems
    simple hardware platform
    microcontrollers
    Opis:
    This paper presents the simple distributed system hardware platform for basic research. It allows to study the different variants and aspects of the data exchange or synchronization methods in distributed systems. Moreover, the platform has the ability to implement distributed embedded systems. The modularity of a system allows for fast reconfiguration of the platform, such as the exchange of end modules. Therefore, it is possible to make quick changes and verify the system operation.
    Źródło:
    Measurement Automation Monitoring; 2015, 61, 2; 47-50
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Some Schemes for Implementation of Arithmetic Operations with Complex Numbers Using Squaring Units
    Autorzy:
    Cariow, A.
    Cariowa, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/114347.pdf
    Data publikacji:
    2017
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    complex number arithmetic
    squaring unit
    implementation complexity reduction
    hardware implementation
    Opis:
    In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence of some number of general-purpose binary multipliers. The advantage of our solutions is a removing of multiplications through replacing them by less costly squarers. We use Logan's trick and quarter square technique, which propose to replace the calculation of the product of two real numbers by summing the squares. Replacing usual multipliers with digital squares implies the reducing power consumption as well as decreases the complexity of the hardware circuit. The squarer requiring less area and power as compared to general-purpose multiplier, it is interesting to assess the use of squarers to implementation of complex arithmetic.
    Źródło:
    Measurement Automation Monitoring; 2017, 63, 6; 209-211
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The performance comparison of the DMA subsystem of the Zynq SoC in bare metal and Linux applications
    Autorzy:
    Fularz, M.
    Pieczyński, D.
    Kraft, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/114367.pdf
    Data publikacji:
    2017
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    FPGA
    image processing
    hardware accelerator
    smart camera
    operating system
    Opis:
    The paper presents results of comparison of the direct memory access (DMA) performance in a Zynq SoC based system working in a bare metal configuration and running the Linux operating system (OS). The overhead introduced by the driver and software components of the Linux OS is evaluated and analyzed. The evaluation is performed on a real life video processing usage scenario involving transfers of significant portions of data to- and from the memory.
    Źródło:
    Measurement Automation Monitoring; 2017, 63, 5; 189-191
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An Universal USB 3.0 FIFO Interface For Data Acquisition
    Autorzy:
    Mroczek, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/114677.pdf
    Data publikacji:
    2016
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    data acquisition
    USB 3.0
    SuperSpeed
    FPGA
    hardware interface
    Opis:
    In this paper, an USB – DAQ interface unit that allows connecting data acquisition (DAQ) application to USB is presented. The unit contains two main components: USB to FIFO IC controller and application controller, designed as VHDL core for FPGA. DAQ logic can be connected to USB through simple I/O and streaming interfaces, thus development time of user application can be reduced. The design was tested with high-speed and SuperSpeed FTDI and Cypress USB – FIFO controllers.
    Źródło:
    Measurement Automation Monitoring; 2016, 62, 12; 434-438
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Basic Aspects of Designing a High-performance Processor Structure for Calculating a "true" Discrete Fractional Fourier Transform
    Autorzy:
    Cariow, A.
    Majorkowska-Mech, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/114579.pdf
    Data publikacji:
    2018
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    discrete fractional Fourier transform
    parallelization of computations
    hardware implementation
    complexity reduction
    Opis:
    This paper presents a basic aspects of structural design of the highperformance processor for implementation of discrete fractional Fourier transform (DFrFT). The general idea of the possibility of parallelizing the calculation of the so-called “true” discrete Fourier transform on the basis of our previously developed algorithmic approach is presented. We specifically focused only on the general aspects of the organization of the structure of such a processor, since the details of a particular implementation always depend on the implementation platform used, while the general idea of constructing the structure of the processor remains unchanged.
    Źródło:
    Measurement Automation Monitoring; 2018, 64, 2; 43-45
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Estimation of Wide-Lane Hardware Delays for single station in GPS system
    Autorzy:
    Krasuski, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/114516.pdf
    Data publikacji:
    2015
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    GPS
    Wide-Lane Hardware Delays
    Melbourne-Wübbena linear combination
    Local Ionosphere Monitoring System
    Opis:
    The paper presents study results about determination Wide-Lane Hardware Delays in GPS system. For this purpose GPS data from RYKI reference station were used. Melbourne-Wübbena linear combination were applied for estimation WHD. Computations were executed in SciTEC software, which code source was written in Scilab 5.4.1. Firstly, results from SciTEC software show that WHD are very stable over few days. In this paper 4 experiments are presented. Accuracy of WHD in submitted paper is less than 2 ns. Over few days, magnitude order of mean SWHD is ± 1 ns, what corresponds to 0.3 cycle of wavelength in L6 combination. Difference between maximum and minimum value of SWHD over 6 days is about ± 2.5 ns. RWHD over few days are so very stable, with mean value about 0.154 ns. Standard deviation of daily repeatability RWHD parameter is less than 0.07 ns, what corresponds to 2% of wavelength in L6 combination.
    Źródło:
    Measurement Automation Monitoring; 2015, 61, 1; 5-8
    2450-2855
    Pojawia się w:
    Measurement Automation Monitoring
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-11 z 11

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