Autor: Domański, A. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: A model of partially-depleted SOI MOSFETs in the subthreshold range
Autorzy:: Tomaszewski, D.
Łukasiak, L.
Jakubowski, A.
Domański, K.
Powiązania:: https://bibliotekanauki.pl/articles/308425.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI MOSFET
subthreshold range
floating body
transconductance
Opis:: A steady-state model of partially-depleted (PD) SOI MOSFETs I-V characteristics in subthreshold range is presented. Phenomena, which must be accounted for in current continuity equation, which is a key equation of the PD SOI MOSFETs model are summarized. A model of diffusion-based conduction in a weakly-inverted channel is described. This model takes into account channel length modulation, drift of carriers in the "pinch-off" region and avalanche multiplication triggered by these carriers. Characteristics of the presented model are shown and briefly discussed.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 61-64
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: A versatile tool for extraction of MOSFETs parameters
Autorzy:: Tomaszewski, D.
Kociubiński, A.
Marczewski, J.
Kucharski, K.
Domański, K.
Grabiec, P.
Powiązania:: https://bibliotekanauki.pl/articles/308856.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: MOSFETs parameters
SPICE
least squares method
Opis:: Extraction of MOSFET parameters is a very important task for the purposes of MOS integrated circuits characterization and design. A versatile tool for the MOSFET parameter extraction has been developed in the Institute of Electron Technology (IET). It is used to monitor the technologies applied for fabrication of several groups of devices, e.g., CMOS ASICs, SOI pixel detectors. At present two SPICE MOSFET models (LEVEL = 1, 2) have been implemented in the extraction tool. The LEVEL = 3 model is currently being implemented. The tool combines different methods of parameter extraction based on local as well as global fitting of models to experimental data.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 129-134
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Network-on-Multi-Chip (NoMC) with Monitoring and Debugging Support
Autorzy:: Łuczak, A.
Stępniewski, M.
Siast, J.
Domański, M.
Stankiewicz, O.
Kurc, M.
Konieczny, J.
Powiązania:: https://bibliotekanauki.pl/articles/307888.pdf
Data publikacji:: 2011
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: debugging
FPGA
multi-chip
video coding
Opis:: This paper summarizes recent research on network-on-multi-chip (NoMC) at Poznań University of Technology. The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A multicast transmission also enables real-time packet monitoring. The introduced features of NoC network allow to elaborate a model of hardware video codec that utilizes distributed processing on many FPGAs. Final performance of the designed network was assessed using a model of AVC coder and multi-FPGA platforms. In such a system, the introduced multicast transmission mode yields overall gain of bandwidth up to 30%. Moreover, synthesis results show that the basic network components designed in Verilog language are suitable and easily synthesizable for FPGA devices.
Źródło:: Journal of Telecommunications and Information Technology; 2011, 3; 81-86
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Piezoresistive sensors for atomic force microscopy - numerical simulations by means of virtual wafer fab
Autorzy:: Dębski, T.
Barth, W.
Rangelow, I.W.
Domański, K.
Tomaszewski, D.
Grabiec, P.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/307644.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: atomic force microscopy (AFM)
piezoresistive sensors
technology simulation
technology characterization
Opis:: An important element in microelectronics is the comparison of the modelling and measurements results of the real semiconductor devices. Our paper describes the final results of numerical simulation of a micromechanical process sequence of the atomic force microscopy (AFM) sensors. They were obtained using the virtual wafer fab (VWF) software, which is used in the Institute of Electron Technology (IET). The technology mentioned above is used for fabrication of the AFM cantilevers, which has been designed for measurement and characterization of the surface roughness, the texturing, the grain size and the hardness. The simulation are very useful in manufacturing other microcantilever sensors.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 35-39
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: TSSOI as an efficient tool for diagnostics of SOI technology in Institute of Electron Technology
Autorzy:: Barański, M.
Domański, K.
Grabiec, P.
Grodner, M.
Jaroszewicz, B.
Kociubiński, A.
Kucewicz, W.
Kucharski, K.
Marczewski, J.
Niemiec, H.
Sapor, M.
Tomaszewski, D.
Powiązania:: https://bibliotekanauki.pl/articles/308825.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: SOI CMOS technology
pixel detector
test structure
Opis:: This paper reports a test structure for characterization of a new technology combining a standard CMOS process with pixel detector manufacturing technique. These processes are combined on a single thick-_lm SOI wafer. Preliminary results of the measurements performed on both MOS SOI transistors and dedicated SOI test structures are described in detail.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 85-93
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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