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    Wyświetlanie 1-6 z 6
    Tytuł:
    Design of a 3rd order 1.5-bit continuous-time (CT) sigma-delta (ΣΔ) modulator optimized for class D audio power amplifier
    Autorzy:
    de Melo, J.
    Paulino, N.
    Powiązania:
    https://bibliotekanauki.pl/articles/398039.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    czas ciągły sigma-delta(ΣΔ)
    wzmacniacz klasy D
    audio
    Continuous-Time(CT) Sigma-Delta(ΣΔ)
    class D amplifier
    Opis:
    This paper presents a 3rd order 1.5-bit ΣΔ modulator with distributed feedback and local resonator feedback for a Class D audio amplifier. In order to improve the signal-to-noise-and-distortion ratio (SNDR), without increasing the oversampling ratio (OSR) or the order of the modulator, the modulator uses transmission zeros and 1.5-bit quantization. High level simulations of the modulator architecture show that it has a maximum SNDR value of 81 dB, for a signal bandwidth of 18 kHz and a sampling frequency of 1.2 MHz. An electrical circuit is designed to implement the proposed architecture and the electrical simulations show that it has a maximum SNDR value of 76.1 dB. The influence of the constituting blocks of the circuit in the performance of the modulator is investigated using electrical simulations.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 2; 156-164
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Evolutionary optimization of Sigma-Delta modulated analog stimulus
    Autorzy:
    Golonek, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/397702.pdf
    Data publikacji:
    2015
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    analog electronic circuits testing
    evolutionary optimization
    sigma-delta modulation
    pulse density modulation
    analogowy układ elektroniczny
    optymalizacja ewolucyjna
    modulacja sigma-delta
    modulacja gęstości impulsów
    Opis:
    This paper proposes the evolutionary technique of the stimulus signal optimization for the analog electronic circuit testing purpose. The obtained signal is coded with Sigma-Delta modulation usage that allows to generate it easily by simple microcontrollers without the necessity of expensive D/A peripherals applying. The signal with the controlled impulses density may be obtained on the external output terminal of the typical timer and finally, it defines the analog signal that can be reconstructed after low pass filtering.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2015, 6, 4; 130-135
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs
    Autorzy:
    Abdollahvand, S.
    Goes, J.
    Paulino, N.
    Gomes, L.
    Powiązania:
    https://bibliotekanauki.pl/articles/397961.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    filtr decymacyjny
    filtr wielofazowy
    modulator sigma-delta
    field-programmable gate array
    FPGA
    decimation filter
    Polyphase Comb filter
    sigma-delta modulators
    field programmable gate array (FPGA)
    Opis:
    This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 4; 152-158
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Measurement and performance evaluation of a silicon on insulator pixel matrix
    Autorzy:
    Ntavelis, D.
    Harik, L.
    Sallese, J.-M.
    Kayal, M.
    Hatzopoulos, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/397821.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    technika SOI tranzystora polowego MOS
    czujnik obrazu
    pompować ładunek
    pierwsza kolejność delta-sigma
    SOI MOSFET
    image sensors
    charge pumping
    first order delta-sigma
    Opis:
    A new technique for driving silicon-on-insulator pixel matrixes has been proposed in |1|, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8x8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with results of its implementation on the fabricated pixel matrix. The results show the applicability of the charge pumping technique and the effective operation of the image sensor.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 3; 299-304
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis and Design of a First - Order Delta-Sigma Modulator based on Ultra Incomplete Settling and Considering Non-ideal Effects
    Autorzy:
    Nowacki, B.
    Paulino, N.
    Goes, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/397918.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    modulator Delta-Sigma
    integrator bierny
    konwersja analogowo-cyfrowa
    konwersja A/D
    filtr S.C.
    delta-sigma modulator
    passive integrator
    analog-to-digital conversion
    A/D conversion
    passive SC filter
    Opis:
    One of the main building blocks of a Delta-Sigma modulator (ΔΣ?) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣcircuit based on the implementation of passive switched-capacitor (SC) integrator using ultra incomplete settling. The behavior of a 1st order ΔΣ? is fully analyzed and explained, as well as its non-ideal effects, which become more significant for higher clock frequencies. This work compares performance of ΔΣM clocked with Fclk=100 MHz and Fclk=300 MHz. Electrical simulations show that the ΔΣM (Fclk=300 MHz) achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 67.5 dB, a peak signal-to-noise ratio (SNR) of 69.7 dB for a signal with a bandwidth (BW) of 400 kHz, while dissipating only 232μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 165 fJ/conv.-step (simulated).
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 4; 125-131
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Estimating the noise-related error in continuous-time integrator-based ADCs
    Autorzy:
    Gosselin, P.
    Koukab, A.
    Kayal, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/398023.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    noise
    white noise
    flicker noise
    error
    accuracy
    standard deviation
    variance
    integrator-based ADC
    incremental
    Sigma-Delta
    szum
    szum biały
    fliker-szum
    błąd
    dokładność
    odchylenie standardowe
    wariancja
    ADC
    Opis:
    From first-order incremental ΣΔ converters to controlled-oscillator-based converters, many ADC architectures are based on the continuous-time integration of the input signal. However, the accuracy of such converters cannot be properly estimated without establishing the impact of noise. In fact, noise is also integrated, resulting in a random error that is added to the measured value. Since drifting phenomena may make simulations and practical measurements unable to ensure longterm reliability of the converters, a theoretical tool is required. This paper presents a solution to compute the standard deviation of the noise-generated error in continuous-time integrator-based ADCs, under the assumption that a previous measure is used to calibrate the system. In addition to produce a realistic case, this assumption allows to handle a theoretical issue that made the problem not properly solvable. The theory is developed, the equations are solved in the cases of pure white noise, pure flicker noise and low-pass filtered white noise, and the implementation issues implied by the provided formulas are addressed.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 2; 54-59
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-6 z 6

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