Autor: Hatzopoulos, A. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Interconnections coupling through substrate for frequencies up to 100 GHz
Autorzy:: Gerakis, V
Hatzopoulos, A.
Powiązania:: https://bibliotekanauki.pl/articles/397752.pdf
Data publikacji:: 2014
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: substrate noise
interconnect coupling
substrate doping
S-parameters
Z-parameters
zakłócenia podłożowe
domieszkowanie substratu
parametry rozproszenia
parametry impedancji
Opis:: This work presents a study on the substrate noise coupling between two interconnects. A highly, a lightly and a uniformly doped substrate, approximating most modern technologies, are described. The three different doping profiles are simulated for various interconnect distances and different metal layers assuming a 65 nm bulk CMOS technology. A proper data analysis methodology is presented, including z and s parameters extraction and de-embedding procedure.
Źródło:: International Journal of Microelectronics and Computer Science; 2014, 5, 4; 144-148
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Wavelet energy-based mahalanobis distance metric for testing analog and mixed-signal circuits
Autorzy:: Spyronasios, A. D.
Dimopoulos, M. G.
Hatzopoulos, A. A.
Powiązania:: https://bibliotekanauki.pl/articles/398112.pdf
Data publikacji:: 2010
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: analogowy i mieszany test sygnału
test obwodu
falki
odległość Mahalanobisa
Analog and Mixed-Signal Testing
Circuit Test
wavelets
Mahalanobis distance
Opis:: In this paper a test method based on the wavelet transformation of the measured signal, be it supply current (Ips) or output voltage (Vout) waveform, is presented. In the wavelet analysis, a Mahalanobis distance test metric is introduced utilizing information from the wavelet energies of the first decomposition level of the measured signal. The tolerance limit for the good circuit is set by statistical processing data obtained from the fault-free circuit. Simulation comparative results on benchmark circuits for testing both hard faults and parametric faults are presented showing the effectiveness of the proposed testing scheme.
Źródło:: International Journal of Microelectronics and Computer Science; 2010, 1, 2; 218-224
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 3.

Tytuł:: Automated substrate resistance extraction in nanoscale VLSI by exploiting a geometry-based analytical model
Autorzy:: Bontzios, Y. I.
Dimopoulos, M. G.
Hatzopoulos, A. A.
Powiązania:: https://bibliotekanauki.pl/articles/398110.pdf
Data publikacji:: 2011
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: szum podłożowy
układ scalony
modelowanie geometryczne
pochodzenie oporu
modelowanie oporu
zasilanie pasożytnicze
substrate noise
integrated circuits
geometric modeling
resistance extraction
resistance modeling
parasitics
Opis:: In this work, a new automated method for determining the substrate resistance is presented. It exploits a geometric formulation of the current streamlines between coupled structures and builds an analytical model for the substrate resistance. Both simulation and measurement data are utilized in order to show the validity of the proposed scheme. The measurement data are obtained from a fabricated test chip. The results show that the proposed method succeeds in computing the substrate resistance while the average error falls within 5%.
Źródło:: International Journal of Microelectronics and Computer Science; 2011, 2, 3; 81-87
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 4.

Tytuł:: Measurement and performance evaluation of a silicon on insulator pixel matrix
Autorzy:: Ntavelis, D.
Harik, L.
Sallese, J.-M.
Kayal, M.
Hatzopoulos, A.
Powiązania:: https://bibliotekanauki.pl/articles/397821.pdf
Data publikacji:: 2010
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: technika SOI tranzystora polowego MOS
czujnik obrazu
pompować ładunek
pierwsza kolejność delta-sigma
SOI MOSFET
image sensors
charge pumping
first order delta-sigma
Opis:: A new technique for driving silicon-on-insulator pixel matrixes has been proposed in |1|, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8x8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with results of its implementation on the fabricated pixel matrix. The results show the applicability of the charge pumping technique and the effective operation of the image sensor.
Źródło:: International Journal of Microelectronics and Computer Science; 2010, 1, 3; 299-304
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

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