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Wyszukujesz frazę "CMOS technology" wg kryterium: Temat

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    Wyświetlanie 1-6 z 6
    Tytuł:
    TSSOI as an efficient tool for diagnostics of SOI technology in Institute of Electron Technology
    Autorzy:
    Barański, M.
    Domański, K.
    Grabiec, P.
    Grodner, M.
    Jaroszewicz, B.
    Kociubiński, A.
    Kucewicz, W.
    Kucharski, K.
    Marczewski, J.
    Niemiec, H.
    Sapor, M.
    Tomaszewski, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/308825.pdf
    Data publikacji:
    2005
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    SOI CMOS technology
    pixel detector
    test structure
    Opis:
    This paper reports a test structure for characterization of a new technology combining a standard CMOS process with pixel detector manufacturing technique. These processes are combined on a single thick-_lm SOI wafer. Preliminary results of the measurements performed on both MOS SOI transistors and dedicated SOI test structures are described in detail.
    Źródło:
    Journal of Telecommunications and Information Technology; 2005, 1; 85-93
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design and analysis of MOS based Magnetic Field Sensor
    Autorzy:
    Kumar, Rakesh
    Powiązania:
    https://bibliotekanauki.pl/articles/1075557.pdf
    Data publikacji:
    2019
    Wydawca:
    Przedsiębiorstwo Wydawnictw Naukowych Darwin / Scientific Publishing House DARWIN
    Tematy:
    CMOS Technology
    Hall Effect
    Lorentz force
    MagFET device
    Magnetic sensor
    Opis:
    Magnetic sensors are widely used in various applications such as consumer electronic products (mobile phones, laptops), biomedical applications (brain function mapping), navigation, vehicle detection, mineral prospecting, non-contact switching (keyboard), contactless temperature measurement, wireless sensor network etc. Sensitivity of MagFET devices towards magnetic field, depends on the shape, dimensions VGS, VDS. In this paper we have measured effect of Physical design of gate on sensitivity of MagFET.
    Źródło:
    World Scientific News; 2019, 121; 42-47
    2392-2192
    Pojawia się w:
    World Scientific News
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multiple output CMOS current amplifier
    Autorzy:
    Pankiewicz, B.
    Powiązania:
    https://bibliotekanauki.pl/articles/201141.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    current amplifier
    current follower
    current mirror
    CMOS technology
    wzmacniacz prądowy
    prąd
    technologia CMOS
    Opis:
    In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 2; 301-306
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Designing Method of Compact n-to-2ⁿ Decoders
    Autorzy:
    Brzozowski, I.
    Zachara, Ł.
    Kos, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226116.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    decoder
    address decoder
    standard cell
    layouts design
    CMOS technology
    power dissipation
    power consumption
    delay
    Opis:
    What decoder is, everyone knows. The paper presents fast and efficient method of layouts design of n-to-2ⁿ -lines decoders. Two scenarios of layout arrangement are proposed and described. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library. Moreover, some important parameters, such area, power dissipation and delay, were assessed and compared for decoders designed with proposed method and traditional. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. All designs were done in UMC 180 CMOS technology.
    Źródło:
    International Journal of Electronics and Telecommunications; 2013, 59, 4; 405-413
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells
    Autorzy:
    Kushwaha, P.
    Chaudhry, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308384.pdf
    Data publikacji:
    2011
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    5T SRAM
    65 nm CMOS technology
    6T SRAM
    7T SRAM
    low power SRAM
    power reduction technique
    Opis:
    In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.
    Źródło:
    Journal of Telecommunications and Information Technology; 2011, 4; 124-130
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Projekt scalonego wzmacniacza ładunkowego na potrzeby przetwarzania typu Time-over-Threshold
    Design of the integrated charge-sensitive amplifier for the Time-over-Threshold based processing
    Autorzy:
    Kasiński, K.
    Szczygieł, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/157771.pdf
    Data publikacji:
    2010
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    układ scalony
    technologia CMOS
    krzemowy detektor paskowy Time-over-Threshold
    wzmacniacz ładunkowy
    integrated circuit
    CMOS technology
    silicon strip detector
    Time-over-Threshold
    charge sensitive amplifier
    CSA
    Opis:
    Praca przedstawia projekt scalonego wzmacniacza ładunkowego zaprojektowanego dla aplikacji w układzie do odczytu detektorów paskowych w eksperymencie fizyki wysokich energii wykorzystującego przetwarzanie typu Time-over-Threshold. Zastosowane rozwiązania zostały zapożyczone z układów pikselowych. Projekt wykonano dla technologii United Microelectronics Corporation 180 nm. Zaprojektowany wzmacniacz charakteryzuje się niskim poborem mocy, niskimi szumami a także bardzo szerokim zakresem liniowej pracy zachowując swoje właściwości dla obu polarności ładunków wejściowych.
    New High Energy Physics experiments require new and better solutions for the detector readout systems. This paper presents the project of the charge sensitive amplifier (CSA) for the silicon strip detector readout chip implementing the Wilkinson-type analog to digital converter (called also Time-over-Threshold processing). This allows to implement the reasonable resolution and speed ADC in each channel while keeping the overall power consumption low. This is due to the fact that the information about the input charge is kept in the CSA output pulse length and can be then easily converted to digital domain. It has been designed for the UMC (United Micro-electronics Corporation) 180nm technology and should fit into 50 Μm pitch channel slot. Some solutions were adapted from the pixel-oriented integrated circuits and are optimized for much higher detec-tor capacitances. Presented charge sensitive amplifier shows very high dynamic range - much higher than required 0-16 fC. The dynamic range is not limited by the dynamic range of the amplifier itself which is a feature of the implemented discharge circuit. The processing chain has an ability to operate for both holes and electrons while keeping the low power consumption (625 ΜW) and low noise (720 e- at 30 pF detector capacitance). The paper presents the simulation-based performance of the circuit.
    Źródło:
    Pomiary Automatyka Kontrola; 2010, R. 56, nr 9, 9; 1043-1046
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-6 z 6

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