Temat: deep submicron - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Reliability of deep submicron MOSFETs
Autorzy:: Balestra, F.
Powiązania:: https://bibliotekanauki.pl/articles/307658.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: bulk MOSFETs
SOI devices
deep submicron
transistors
reliability
Opis:: In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature is given. The main hot carrier effects and degradation are compared for bulk and SOI devices in a wide range of gate length, down to deep submicron. The worst case aging, defice lifetime and maximum drain bias that can be applied are addressed. The physical mechanisms and the emergence of new phenomena at the origin of the degradation are studied for advanced MOS transistors. The impact of the substrate bias is also outlined.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 12-17
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Readout Electronics for Pixel Detectors in Deep Submicron and 3D Technologies
Autorzy:: Maj, P.
Szczygieł, R.
Gryboś, P.
Powiązania:: https://bibliotekanauki.pl/articles/227192.pdf
Data publikacji:: 2011
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: hybrid pixel detectors
deep submicron technology
3D
Opis:: We have designed, fabricated in 90 nm technology and tested a prototype ASIC for readout of semiconductor pixel detectors for X-ray imaging applications. The 4mm x 4mm readout IC is working in single photon counting mode and contains a pixel matrix of 1280 readout channels with dimensions of 100 µm × 100 µm each. We present the architecture, the measurement results of this IC and our conclusions. To make this chip more attractive for novel experiments, we need to further increase single pixel functionality and at the same time reduce the pixel area. This leads us to the 3D technology with at least two layers: analogue and digital and additionally the sensor layer. We present the concept of the 3D hybrid pixel chip design with small pixel size and the ability to build a dead-space free large area pixel matrix.
Źródło:: International Journal of Electronics and Telecommunications; 2011, 57, 4; 497-502
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Layout Optimizations of Operational Amplifiers in Deep Submicron
Autorzy:: Shi, Jun
Powiązania:: https://bibliotekanauki.pl/articles/226453.pdf
Data publikacji:: 2020
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: Layout Optimization
deep submicron (DSM)
Operational Amplifier
place-and-route
Opis:: Operational amplifies (op amps) are an integral part of many analog and mixed-signal systems. Op amps with vastly different levels of complexity are used to realize functions ranging from DC bias generation to high-speed amplification or filtering. The design of op amps continues to pose a challenge as the supply voltage and transistor channel lengths scale down with each generation of CMOS technologies. The thesis deals with the analysis, design and layout optimization of CMOS op amps in deep Submicron (DSM) from a study case. Finally, layout optimizations of op amps will be given, in which propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design.
Źródło:: International Journal of Electronics and Telecommunications; 2020, 66, 2; 287-293
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Advanced compact modeling of the deep submicron technologies
Autorzy:: Grabiński, W.
Bucher, M.
Sallese, J.-M.
Krummenacher, F.
Powiązania:: https://bibliotekanauki.pl/articles/309312.pdf
Data publikacji:: 2000
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: ultra deep submicron (UDSM) technology
compact modeling
EKV MOS transistor model
MOSFET
matching
low power
RF applications
Opis:: The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 žm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model
Źródło:: Journal of Telecommunications and Information Technology; 2000, 3-4; 31-42
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Methodology for the digital calibration of analog circuits and systems using sub-binary radix DACs
Autorzy:: Pastre, M.
Kayal, M
Powiązania:: https://bibliotekanauki.pl/articles/397857.pdf
Data publikacji:: 2010
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: wzorcowanie
sub binarny DACs
przeniesienie kompensancji
głębokie sub mikrony
zmienność
calibration
sub-binary DACs
M/2+M
offset compensation
deep submicron
variability
Opis:: This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub-binary radix M/2+M DAC, which has the advantage of allowing reaching arbitrarily high resolutions at the cost of extremely small area. The methodology proposed allows the removal of any type of imperfections, at the expense of two shift registers, a few logical gates and a DAC which is smaller than the shift register.
Źródło:: International Journal of Microelectronics and Computer Science; 2010, 1, 1; 25-30
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

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