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Wyszukujesz frazę "EKV" wg kryterium: Temat


Wyświetlanie 1-6 z 6
Tytuł:
Large-Signal RF Modeling with the EKV3 MOSFET Model
Autorzy:
Chalkiadaki, M. A.
Buchar, M.
Powiązania:
https://bibliotekanauki.pl/articles/308061.pdf
Data publikacji:
2010
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
compact model
EKV3 model
large-signal
load-pull
MOSFET model
radio frequency
Opis:
This paper presents a validation of the EKV3 MOSFET model under load-pull conditions with high input power at 5.8 GHz, as well as S-parameter measurements with low input power up to 20 GHz. The EKV3 model is able to represent coherently the large- and small-signal RF characteristics in advanced 90 nm CMOS technology. Multifinger devices with nominal drawn gate length of 70 nm are used.
Źródło:
Journal of Telecommunications and Information Technology; 2010, 1; 29-33
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
BSIM3v3 to EKV2.6 Model Parameter Extraction and Optimisation using LM Algorithm on 0.18μ Technology node
Autorzy:
Singh, K.
Jain, P.
Powiązania:
https://bibliotekanauki.pl/articles/226194.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
EKV2.6
BSIM3v3
specific current IS
optimisation
LM algorithm
Opis:
The industry standard BSIM3v3 and BSIM4.0 have been replaced by BSIM6.0 compact MOSFET model for deep submicron technology node. The BSIM6.0 is next generation, defacto industry standard model for bulk MOSFET. This model is charge based which is continuous from weak to strong inversion of operation. The core of analytical and physical BSIM6 model[3] is charge, with drain current equation expressed in form of source(qs) and drain charge(qd). This model has all its governing equations continuous and can be used to develop design methodology using IC based approach. But its method of computing qs and qd is complicated which is different from Vittoz traditional charge calculation method. The continuous interpolation equation of drain current as adopted by EKV2.6 although is empirical but its compact expression is preferred by analog designer to get intuitive design guidance. BSIM6 is a combined effort by BSIM and EKV modeling groups based on charge based continuous equations. Although EKV2.6 model is not valid for deep submicron process as it only includes submicron short channel effects like velocity saturation (VS), vertical field mobility reduction (VFMR), Drain induced barrier lowering (DIBL), channel length modulation (CLM) etc. But it still offers some benefits to have first cut design methodology because of its much simplified analytical equations. The inversion coefficient (IC) has found extensive acceptance in designer community as it offers enhanced design elegance in EKV then more complicated BSIM model. This paper discuses first step in analog design process by extracted core EKV2.6 intrinsic model parameters from industry standard BSIM3v3 model on 0.18μ technology node. The 0.18μ technology is chosen as it is still more common technology node in analog circuit design. The model parameters are extracted for different bins and optimisation is done using nonlinear optimisation LM algorithm. The optimised EKV2.6 parameters are validated with current-voltage (I-V), intrinsic voltage gain (Avi) and Early voltage circuit parameter (VA) with BSIM3v3 model.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 1; 5-11
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Adaptive EPFL-EKV Long and Short Channel MOS Device Models for Qucs, SPICE and Modelica Circuit Simulation
Autorzy:
Brinson, M. E.
Nabijou, H.
Powiązania:
https://bibliotekanauki.pl/articles/398007.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
model adaptacyjny MOS
Qucs
SPICE
Modelica
monitoring parametru
adaptive MOS models
equation-defined device modelling
Verilog-A
EPFL-EKV MOS-FET model
parameter and equation monitoring
EPFL-EKV MOS-FET
Opis:
Equation-defined non-linear functional elements are important building blocks in the development of compact semiconductor device models. Current trends in compact device modelling suggest widespread acceptance among the modeling community of Verilog-A, for semiconductor device specification, model exchange and circuit simulation. This paper outlines techniques for the development of adaptive EPFL-EKV long and short channel MOS models which stress user selectable model features and diagnostic capabilities. Adaptive EPFL-EKV nMOS models based on Verilog-A and Modelica are introduced and their performance compared with simulation data obtained using the "Quite universal circuit simulator" (Qucs), SPICE and the Modelica simulation environment.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 1; 1-6
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold
Autorzy:
Kalra, S.
Bhattacharyya, A. B.
Powiązania:
https://bibliotekanauki.pl/articles/226500.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
energy efficiency
ultra-low power
EKV
minimum energy point
minimum delay point temperature to time generator
Opis:
Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 4; 369-374
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Advanced compact modeling of the deep submicron technologies
Autorzy:
Grabiński, W.
Bucher, M.
Sallese, J.-M.
Krummenacher, F.
Powiązania:
https://bibliotekanauki.pl/articles/309312.pdf
Data publikacji:
2000
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
ultra deep submicron (UDSM) technology
compact modeling
EKV MOS transistor model
MOSFET
matching
low power
RF applications
Opis:
The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 žm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model
Źródło:
Journal of Telecommunications and Information Technology; 2000, 3-4; 31-42
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
An accurate prediction of high-frequency circuit behaviour
Autorzy:
Yoshitomi, S.
Kimijima, H.
Kojima, K.
Kokatsu, H.
Powiązania:
https://bibliotekanauki.pl/articles/308807.pdf
Data publikacji:
2005
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
electro-magnetic simulation
SPICE
circuit test structure
RF CMOS
EKV2.6-MOS model
spiral inductor
CMOS VCO
Opis:
An accurate way to predict the behaviour of an RF analogue circuit is presented. A lot of effort is required to eliminate the inaccuracies that may generate the deviation between simulation and measurement. Efficient use of computer-aided design and incorporation of as many physical effects as possible overcomes this problem. Improvement of transistor modelling is essential, but there are many other unsolved problems affecting the accuracy of RF analogue circuit modelling. In this paper, the way of selection of accurate transistor model and the extraction of parasitic elements from the physical layout, as well as implementation to the circuit simulation will be presented using two CMOS circuit examples: an amplifier and a voltage controlled oscillator (VCO). New simulation technique, electro-magnetic (EM)-co-simulation is introduced.
Źródło:
Journal of Telecommunications and Information Technology; 2005, 1; 47-62
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-6 z 6

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