Autor: Szecówka, P. M. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Fuzzy Processing Implementation in Dedicated Digital Hardware
Autorzy:: Szecówka, P. M.
Musiał, A.
Powiązania:: https://bibliotekanauki.pl/articles/226691.pdf
Data publikacji:: 2010
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: fuzzy
hardware
floating point
VHDL
FPGA
Opis:: The paper presents a concept of digital circuit dedicated for fuzzy processing with numerical inputs and outputs. Partially concurrent and pipelined data flow provides high performance, with relatively low dependence on particular algorithm complexity. Sample design with triangular fuzzy sets, rule strength calculation (minimum approach) and defuzzyfication by weighted sum of fuzzy sets centers was implemented in VHDL, verified and synthesized for FPGA. Floating point arithmetic was applied, including dvision performed by dedicated synchronous machine. All modules were prepared for easy reuse/redesign.
Źródło:: International Journal of Electronics and Telecommunications; 2010, 56, 4; 405-410
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Dedicated Digital Hardware for DVB-CSA Encryption
Autorzy:: Szecówka, P. M.
Marucha, P. W.
Powiązania:: https://bibliotekanauki.pl/articles/227134.pdf
Data publikacji:: 2012
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: DVB-CSA
digital video broadcasting
Common Scrambling Algorithm
encryption
hardware
VHDL
FPGA
Opis:: DVB-CSA (Digital Video Broadcast - Common Scrambling Algorithm) is encryption method commonly used to protect the paid channels of digital television. The paper presents a study of its implementation in specialized digital hardware. The algorithm was successfully converted to logic architecture, coded in hardware description language (VHDL), verified and synthesized for programmable logic device (FPGA). For Xlinx Spartan 3 implementation, the expected throughput may be estimated to 100 Mbps in pipelined mode.
Źródło:: International Journal of Electronics and Telecommunications; 2012, 58, 3; 241-246
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

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