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    Wyświetlanie 1-4 z 4
    Tytuł:
    Automatic parametric fault detection in complex analog systems based on a method of minimum node selection
    Autorzy:
    Bilski, A.
    Wojciechowski, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/330761.pdf
    Data publikacji:
    2016
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    complex analog system
    support vector machine (SVM)
    tabu search
    genetic algorithm
    parametric fault detection
    system analogowy
    maszyna wektorów wspierających
    metoda tabu search
    algorytm genetyczny
    detekcja uszkodzeń
    Opis:
    The aim of this paper is to introduce a strategy to find a minimal set of test nodes for diagnostics of complex analog systems with single parametric faults using the support vector machine (SVM) classifier as a fault locator. The results of diagnostics of a video amplifier and a low-pass filter using tabu search along with genetic algorithms (GAs) as node selectors in conjunction with the SVM fault classifier are presented. General principles of the diagnostic procedure are first introduced, and then the proposed approach is discussed in detail. Diagnostic results confirm the usefulness of the method and its computational requirements. Conclusions on its wider applicability are provided as well.
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2016, 26, 3; 655-668
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Soft Fault Clustering in Analog Electronic Circuits with the Use of Self Organizing Neural Network
    Autorzy:
    Grzechca, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/220571.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    fault detection
    parametric faults
    analogue electronic circuits
    self-organizing neural network
    Opis:
    The paper presents a methodology for parametric fault clustering in analog electronic circuits with the use of a self-organizing artificial neural network. The method proposed here allows fast and efficient circuit diagnosis on the basis of time and/or frequency response which may lead to higher production yield. A self-organizing map (SOM) has been applied in order to cluster all circuit states into possible separate groups. So, it works as a feature selector and classifier. SOM can be fed by raw data (data comes from the time or frequency response) or some pre-processing is done at first. The author proposes conversion of a circuit response with the use of e.g. gradient and differentiation. The main goal of the SOM is to distribute all single faults on a two-dimensional map without state overlapping. The method is aimed for the development stage because the tolerances of elements are not taken into account, however single but parametric faults are considered. Efficiency analyses of fault clustering have been made on several examples e.g. a Sallen-Key BPF and an ECG amplifier. Testing procedure is performed in time and frequency domains for the Sallen-Key BPF with limited number of test points i.e. it is assumed that only input and output pins are available. A similar procedure has been applied to a real ECG amplifier in the frequency domain. Results prove a high efficiency in acceptable time which makes the method very convenient (easy and quick) as a first test in the development stage.
    Źródło:
    Metrology and Measurement Systems; 2011, 18, 4; 555-568
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On-chip Parametric Test of R-2R Ladder Digital-to-Analog Converter and Its Efficiency
    Autorzy:
    Arbet, D.
    Stopjakova, V.
    Brenkus, J.
    Gyepes, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/397993.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    wykrywanie uszkodzeń
    uszkodzenie katastroficzne
    uszkodzenia parametryczne
    test parametryczny
    mieszany test sygnału
    fault detection
    catastrophic faults
    parametric faults
    on-chip parametric test
    mixed-signal test
    Opis:
    This paper deals with the investigation of the fault detection in separated parts of a mixed-signal integrated circuit example by implementing parametric test methods. The experimental Circuit Under Test (CUT) consisting of an 8-bit binary-weighted R-2R ladder digital-to-analog converter and additional on-chip test hardware was designed in a standard 0.35 μm CMOS technology. For detection of catastrophic and parametric faults considered in different parts of the CUT, two dedicated parametric test methods: oscillation-based test technique and IDDQ monitoring were used. For the operational amplifier, on-chip and off-chip approaches have been used to compare the efficiency of both approaches in covering catastrophic faults that are hard to detect. For respective converter parts, the excellent fault coverage of 94.21% of hard-detectable faults by the proposed parametric tests was achieved.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 2; 73-80
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Active fault diagnosis based on stochastic tests
    Autorzy:
    Poulsen, N. K.
    Niemann, H.
    Powiązania:
    https://bibliotekanauki.pl/articles/929899.pdf
    Data publikacji:
    2008
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    diagnostyka uszkodzeń
    wykrywanie zmian
    obwód zamknięty
    parametryzacja
    active fault diagnosis
    parametric faults
    stochastic change detection
    closed loop systems
    parametrization
    Opis:
    The focus of this paper is on stochastic change detection applied in connection with active fault diagnosis (AFD). An auxiliary input signal is applied in AFD. This signal injection in the system will in general allow us to obtain a fast change detection/isolation by considering the output or an error output from the system. The classical cumulative sum (CUSUM) test will be modified with respect to the AFD approach applied. The CUSUM method will be altered such that it will be able to detect a change in the signature from the auxiliary input signal in an (error) output signal. It will be shown how it is possible to apply both the gain and the phase change of the output signal in CUSUM tests. The method is demonstrated using an example.
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2008, 18, 4; 487-496
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-4 z 4

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