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Tytuł:
Projekt i implementacja sterowników karty graficznej VGA w układach FPGA
Design and implementation of VGA graphics card in FPGA technology
Autorzy:
Niemojewski, M.
Sapiecha, P.
Powiązania:
https://bibliotekanauki.pl/articles/155616.pdf
Data publikacji:
2007
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
VGA
Video Graphics Adapter
FPGA
field-programmable gate array
Altera
Stratix II
Lancelot VGA
field programmable gate array (FPGA)
Opis:
Celem pracy jest zaprojektowanie interfejsu graficznego i tekstowego umożliwiającego prezentacje informacji na ekranie monitora VGA wykorzystując technologie logicznych układów programowalnych, napisanie sterowników sprzętu dla systemu operacyjnego žClinux oraz przeprowadzenie i analiza wyników testów uzyskanego rozwiązania ze względu na parametry: prędkość rysowania obrazu, stopień obciążenia pamięci.
The paper presents design and implementation of the text and graphics interface for FPGA based system. The article describes VHDL module and video graphics driver for žClinux operating system. The article describes tests of the device. The paper presents possible future work for the design.
Źródło:
Pomiary Automatyka Kontrola; 2007, R. 53, nr 7, 7; 81-83
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
An efficient hardware implementation of a combinations generator
Autorzy:
Mazurkiewicz, T.
Powiązania:
https://bibliotekanauki.pl/articles/298447.pdf
Data publikacji:
2017
Wydawca:
Uniwersytet Warmińsko-Mazurski w Olsztynie
Tematy:
information technology
generator of combinations
field programmable gate array (FPGA)
Opis:
In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.
Źródło:
Technical Sciences / University of Warmia and Mazury in Olsztyn; 2017, 20(4); 405-413
1505-4675
2083-4527
Pojawia się w:
Technical Sciences / University of Warmia and Mazury in Olsztyn
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pulse Sequence Shaper For Radiospectroscopy And Relaxation Methods In NQR
Autorzy:
Bobalo, Y.
Hotra, Z.
Hotra, O.
Politans’kyy, L.
Samila, A.
Powiązania:
https://bibliotekanauki.pl/articles/221794.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
NQR
pulse sequence
field programmable gate array (FPGA)
frequency synthesizer
Opis:
A pulse sequence shaper for the pursuance of the research using a wide spectrum of radiospectroscopy and relaxation methods in NQR is proposed. The distinctive feature of this product is its implementation with the application of a multi-functional programmable frequency synthesizer suitable for high-speed amplitude and phase manipulations.
Źródło:
Metrology and Measurement Systems; 2015, 22, 3; 363-370
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs
Autorzy:
Abdollahvand, S.
Goes, J.
Paulino, N.
Gomes, L.
Powiązania:
https://bibliotekanauki.pl/articles/397961.pdf
Data publikacji:
2012
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
filtr decymacyjny
filtr wielofazowy
modulator sigma-delta
field-programmable gate array
FPGA
decimation filter
Polyphase Comb filter
sigma-delta modulators
field programmable gate array (FPGA)
Opis:
This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.
Źródło:
International Journal of Microelectronics and Computer Science; 2012, 3, 4; 152-158
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
FPGA implementations of low precision floating point multiply-accumulate
Autorzy:
Amaricai, A.
Boncalo, O.
Sicoe, O
Powiązania:
https://bibliotekanauki.pl/articles/397897.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
digital arithmetic
floating point arithmetic
FPGA
field programmable gate array (FPGA)
multiply-accumulate
dot product
arytmetyka cyfrowa
arytmetyka zmiennoprzecinkowa
field-programmable gate array
MAC
iloczyn skalarny
Opis:
Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 4; 159-163
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding
Autorzy:
Bukowiec, A.
Powiązania:
https://bibliotekanauki.pl/articles/227248.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
Boolean algebra
circuit synthesis
field programmable gate array (FPGA)
sequential circuits
Opis:
The method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 1; 35-41
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Calibration of a mixed-signal power network transient stability analysis emulator
Autorzy:
Lanz, G
Fabre, L.
Lilis, G
Kyriakidis, T
Sallin, D
Cherkaoui, R.
Kayal, M.
Powiązania:
https://bibliotekanauki.pl/articles/398094.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
analog computer
calibration
field programmable gate array (FPGA)
FPGA
mixed signal
power system dynamics
komputer analogowy
kalibracja
field-programmable gate array
sygnał mieszany
dynamika systemu elektroenergetycznego
Opis:
The emerging field of power system emulation for real time smart grid management is very demanding in terms of speed and accuracy. This paper provides detailed information about the electronics calibration process of a high-speed power network emulator dedicated to the transient stability analysis of power systems. This emulator uses mixed-signal hardware to model the dynamic behavior of a power network. Special design allows the self-calibration of the analog electronics through successive measurements and correction steps. The calibration operation guarantees high resolution of the transient stability analysis results, so that they can be reliably used for operational planning and control on real power networks.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 4; 142-147
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing
Autorzy:
Łoza, S.
Matuszewski, Ł.
Jessa, M.
Powiązania:
https://bibliotekanauki.pl/articles/963943.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
random numbers
cryptography
ring oscillators
hash functions
field programmable gate array (FPGA)
Opis:
Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.
Źródło:
International Journal of Electronics and Telecommunications; 2015, 61, 2; 199-204
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Digital random bit generators implemented in FPGAs offered by various manufacturers
Autorzy:
Kubczak, P.
Matuszewski, Ł.
Jessa, M.
Łoza, S.
Powiązania:
https://bibliotekanauki.pl/articles/114475.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA)
Opis:
In cryptography, we require that a random sequence should have excellent statistical properties as well as non-deterministic character. Combining multiple independent sources of randomness using the modulo two operation, significantly improves the statistical properties of the generated sequences and also affects the accumulation of true randomness generated in the oscillator sources. This is a very promising method of producing random sequences. In this paper, we compare the implementations of the RO-based combined random generator in various FPGAs technologies offered by various manufactures (Xilinx, Altera, Lattice). In this research, we used a NIST 800-22 statistical test suite to assess the statistical properties. The results show that the method of producing strings with a combined generator is the method stable in terms of technology. The results are similar for implementation in all FPGA used in the experiment. So, the proposed generator can be implemented in various programmable structures together with other components of a cryptographic system.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 293-295
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Zmiennoprzecinkowa jednostka arytmetyczna dla sprzętowej maszyny wirtualnej
A floating point unit for the hardware virtual machine
Autorzy:
Hajduk, Z.
Powiązania:
https://bibliotekanauki.pl/articles/156437.pdf
Data publikacji:
2011
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
układy FPGA
arytmetyka zmiennoprzecinkowa
field programmable gate array (FPGA)
floating point arithmetic
Opis:
W artykule omówiono, opracowaną dla struktur FPGA, implementację układów realizujących podstawowe operacje arytmetyki zmiennoprzecinkowej. Implementacja charakteryzuje się pewnym kompromisem pomiędzy zapotrzebowaniem na zasoby logiczne układu programowalnego a szybkością realizacji operacji arytmetycznych określoną przez liczbę taktów zegara niezbędną do wykonania operacji. Wspomniane układy zostały wykorzystane jako zasadnicze komponenty zmiennoprzecinkowej jednostki arytmetycznej przeznaczonej dla sprzętowej maszyny wirtualnej. Maszyna ta, implementowana w układach FPGA, jest specjalizowanym mikrokontrolerem wykonującym pośredni kod wykonywalny generowany przez kompilator środowiska inżynierskiego CPDev, przeznaczonego do projektowania oprogramowania sterowników przemysłowych. Wykonane testy wydajności maszyny sprzętowej wyposażonej w zmiennoprzecinkową jednostkę arytmetyczną wskazują, że jest ona średnio kilkadziesiąt razy szybsza od dotychczas istniejących realizacji programowych, wykorzystujących popularne mikrokontrolery AVR i ARM.
Under the CPDev (Control Program Developer) engineering environment, programs written in one of the languages defined in the IEC 61131-3 standard are compiled into the universal intermediate code executed on the side of programmable controllers by the virtual machines [9]. There are software implemented virtual machines, dedicated for the platform with popular AVR and ARM microcontrollers, and also there is a recently developed hardware virtual machine implemented using FPGA devices [2]. The hardware virtual machine, which in fact is a specialized microcontroller described in the Verilog Hardware Description Language [3], is several dozen times faster then its software counterparts [2]. But the main drawback of the existing hardware virtual machine is a lack of the ability of executing the floating point computations. The paper presents an architecture of the floating point arithmetic unit accomplishing basic floating point operation, designed for the hardware virtual machine. There are quite a lot of publications concerning FPGA implementation of the floating point arithmetic, for instance [6, 7, 8, 10, 11]. In this paper the realization of basic float-ing point operation, balanced between logic resources requirements and speed of computing (defined by the number of clock cycles necessary to end up a floating point operation), is presented. Figs. 1 and 2 show a simplified micro-architecture of the single precision (according to IEEE 754-1985 standard [5]) floating point multiplier and adder. A floating point divider has roughly the same structure as the multiplier - it differs in states functions performed by some blocks. A few different realizations of the multiplier and adder unit were designed - the details are presented in Tabs. 1 and 3. The general trend is as follows: a shorter clock cycle necessary to execute the operation needs more logic resources of FPGA. A floating point unit for the hardware virtual machine was designed based on the floating point multiplier, divider and adder blocks. Apart from the mentioned above basic floating point operation, the floating point unit also performs operations like: comparison and relation (equals, not equals, more than, more than or equal etc.), absolute value, negation, integer value to floating point value conversion, floating point to integer conversion (rounding, truncating) and some functions fetched from IEC 61131-3 standard like MIN, MAX, LIMIT. To compare performance of the hardware virtual machine equipped with the floating point unit and its software counterparts, the Whetstone based benchmark [1] was written in ST language. The test results are given in Tab. 4. The hardware virtual machine (implemented using Xilinx Spartan 3-AN FPGA XC3S1400AN-4FGG676) is several times faster than the software one implemented on AVR and ARM microcontrollers, and even a little bit faster than the PC based virtual machine (under .NET environment).
Źródło:
Pomiary Automatyka Kontrola; 2011, R. 57, nr 1, 1; 82-85
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Research and Medical Transcranial Doppler System
Autorzy:
Lewandowski, M.
Walczak, M.
Karwat, P.
Witek, B.
Karłowicz, P.
Powiązania:
https://bibliotekanauki.pl/articles/177389.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
Doppler system
digital signal processing
hardware-software partitioning
field programmable gate array (FPGA)
Opis:
A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a numer of spectrograms simultaneously and to reconstruct a flow velocity profile. The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost. The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.
Źródło:
Archives of Acoustics; 2016, 41, 4; 773-781
0137-5075
Pojawia się w:
Archives of Acoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A random number generator using ring oscillators and the Keccak as post-processing
Autorzy:
Łoza, S.
Matuszewski, Ł.
Jessa, M.
Kubczak, P.
Powiązania:
https://bibliotekanauki.pl/articles/114620.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA)
hash function
Opis:
In cryptography, sequences of numbers with unpredictable elements are often required. Such sequences should pass all known statistical tests for random sequences. Because sequences produced in real circuits are biased, they do not pass many statistical tests, e.g., the distribution of numbers is not uniform. Such random number sequences should be subjected to a transformation called post-processing. In this paper, a true random number generator is considered. It uses ring oscillators and the Keccak hash function as post-processing. This paper presents only simulation conditions for this approach since the post-processing part was done using x86 architecture on a PC.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 290-292
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A proposal of output speed multiplication technique for true random number generators based on ring oscillators
Autorzy:
Matuszewski, Ł.
Kubczak, P.
Powiązania:
https://bibliotekanauki.pl/articles/114218.pdf
Data publikacji:
2016
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA)
restart mechanism
Opis:
Nowadays modern cryptographic systems require a tremendous amount of keys. Very fast random number generators (RNGs) are needed to produce those keys in the requested time, but what to do when a solution that is already in use reaches the maximum speed? The aim of the paper is to find the answer to this question. In addition, generated random numbers should not leave a cryptographic system, because according to the Kerckhoffs thesis, the security of the whole system should be based only on a key. The cryptographic system should be enclosed within a single chip. In order to check new ideas and prove them, there were used NIST 800-22 test suite and restarts mechanism. The basic concept of the generator built of ring oscillators is still the same; ring oscillators are combined by XOR gates tree. A single ring oscillator consists of inverter, latch and NAND. This kind of construction provides a tool to make synchronous start and stop of all oscillators and the restart mechanism technique is applied in this manner. The speed of generation was increased by using multiple parallel generator trees to generate instantly the whole n-bit word. The paper shows that reproduction of the base structure is not a simple method of increasing the speed of generator. Moreover, it is always important to carefully consider all new ideas, because even if the NIST statistical test suite is passed, there is a chance that the restart mechanism will show some correlations that can be used during attack on the system.
Źródło:
Measurement Automation Monitoring; 2016, 62, 5; 157-159
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
FPGA realization of an improved alpha max plus beta min algorithm
Autorzy:
Czyżak, M.
Smyk, R.
Powiązania:
https://bibliotekanauki.pl/articles/376709.pdf
Data publikacji:
2014
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
square root computation
alpha max plus beta min algorithm
field programmable gate array (FPGA)
Opis:
The improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. The improved version allows to reduce the peak error from about 4% to 0.33%. This is attained by determination of the approximate ratio of arguments and adequate selection of algorithm coefficients. Four approximation regions are used and hence four sets of coefficients. Also a Xilinx FPGA implementation for 12-bit sign magnitude numbers is shown.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2014, 80; 151-160
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of microprogrammed controllers to be implemented in FPGAs
Autorzy:
Wiśniewski, R.
Barkalov, A.
Titarenko, L.
Halang, W. A.
Powiązania:
https://bibliotekanauki.pl/articles/907791.pdf
Data publikacji:
2011
Wydawca:
Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:
jednostka sterująca
sterownik mikroprogramowany
układ FPGA
control unit
microprogrammed controller
field programmable gate array (FPGA)
Opis:
In the article we propose a new design method for microprogrammed controllers. The traditional structure is improved by modifying internal modules and connections. Such a solution allows reducing the total number of logic elements needed for implementation in programmable structures, especially Field Programmable Gate Arrays (FPGAs). Detailed results of experiments show that on the average the application of the proposed methods yields up to 30% savings as far as the destination device is considered.
Źródło:
International Journal of Applied Mathematics and Computer Science; 2011, 21, 2; 401-412
1641-876X
2083-8492
Pojawia się w:
International Journal of Applied Mathematics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
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