- Tytuł:
- Reducing Leakage Power for SRAM Design Using Sleep Transistor
- Autorzy:
-
Khandelwal, S.
Akashe, S.
Sharma, S. - Powiązania:
- https://bibliotekanauki.pl/articles/1399668.pdf
- Data publikacji:
- 2013-02
- Wydawca:
- Polska Akademia Nauk. Instytut Fizyki PAN
- Tematy:
- 85.40.-e
- Opis:
- Low power design is the industry buzzword these days in present chip design technologies. Caches occupy around 50% of the total chip area and consume considerable amount of power. This project's focus is to reduce leakage power consumption of an 8 kbit SRAM by employing techniques like power gating. The main technique used in power gating is the use of sleep transistor. In our design we have chosen a stack-based implementation.
- Źródło:
-
Acta Physica Polonica A; 2013, 123, 2; 185-187
0587-4246
1898-794X - Pojawia się w:
- Acta Physica Polonica A
- Dostawca treści:
- Biblioteka Nauki
Artykuł