Temat: reconfigurable logic - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Methodology for Implementing Scalable Run-Time Reconfigurable Devices
Autorzy:: Kotynia, Ł.
Amrozik, P.
Napieralski, A.
Powiązania:: https://bibliotekanauki.pl/articles/226469.pdf
Data publikacji:: 2011
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: design reuse
floorplanning
FPGA
implementation
verification
reconfigurable logic
timing analysis
Opis:: The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.
Źródło:: International Journal of Electronics and Telecommunications; 2011, 57, 2; 177-183
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Synthesis and Implementation of Reconfigurable PLC on FPGA Platform
Autorzy:: Milik, A.
Hrynkiewicz, E.
Powiązania:: https://bibliotekanauki.pl/articles/226640.pdf
Data publikacji:: 2012
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: PLC
LD
IL
FPGA
high level synthesis
logic synthesis
arithmetic circuits
reconfigurable hardware
Opis:: The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.
Źródło:: International Journal of Electronics and Telecommunications; 2012, 58, 1; 85-94
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

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