Temat: circuit synthesis - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Optimal SAT Solver Synthesis of Quantum Circuits Representing Cryptographic Nonlinear Functions
Autorzy:: Jagielski, Adam
Powiązania:: https://bibliotekanauki.pl/articles/27311913.pdf
Data publikacji:: 2023
Wydawca:: Polska Akademia Nauk. Czasopisma i Monografie PAN
Tematy:: quantum computing
circuit synthesis
cryptography
satisfiability problem
Opis:: In this article we present a procedure that allows to synthesize optimal circuit representing any reversible function within reasonable size limits. The procedure allows to choose either the NCT or the MCT gate set and specify any number of ancillary qubits to be used in the circuit. We will explore efficacy of this procedure by synthesizing various sources of nonlinearity used in contemporary symmetric ciphers and draw conclusions about properties of those transformations in quantum setting. In particular we will try to synthesize optimal circuit representing ASCON cipher SBOX which recently won NIST competition for Lightweight Cryptography standard.
Źródło:: International Journal of Electronics and Telecommunications; 2023, 69, 2; 261--267
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding
Autorzy:: Bukowiec, A.
Powiązania:: https://bibliotekanauki.pl/articles/227248.pdf
Data publikacji:: 2012
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: Boolean algebra
circuit synthesis
field programmable gate array (FPGA)
sequential circuits
Opis:: The method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.
Źródło:: International Journal of Electronics and Telecommunications; 2012, 58, 1; 35-41
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 3.

Tytuł:: Equivalent diagrams of fractional order elements
Autorzy:: Różowicz, Sebastian
Włodarczyk, Maciej
Zawadzki, Andrzej
Powiązania:: https://bibliotekanauki.pl/articles/27324011.pdf
Data publikacji:: 2023
Wydawca:: Polska Akademia Nauk. Czasopisma i Monografie PAN
Tematy:: fractional order derivative
Laplace transform for fractional order systems
CFE method
circuit synthesis
numerical experiments
Opis:: This paper presents equivalent impedance and operator admittance systems for fractional order elements. Presented models of fractional order elements of the type: sαL,sub>α and 1/sαCsub>α, (0 α 1) were obtained using the Laplace transform based on the expansion of the factor sign to an infinite fraction with varying degrees of accuracy – the continued fraction expansion method (CFE). Then circuit synthesis methods were applied. As a result, equivalent circuit diagrams of fractional order elements were obtained. The obtained equivalent schemes consist both of classical RLC elements, as well as active elements built based on operational amplifiers. Numerical experiments were conducted for the constructed models, presenting responses to selected input signals.
Źródło:: Archives of Control Sciences; 2023, 33, 4; 801--827
1230-2384
Pojawia się w:: Archives of Control Sciences
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 4.

Tytuł:: Many-Valued Gates for Reducing the Chip-Area of Integrated Circuits
Autorzy:: Novikov, S.
Powiązania:: https://bibliotekanauki.pl/articles/92803.pdf
Data publikacji:: 2007
Wydawca:: Uniwersytet Przyrodniczo-Humanistyczny w Siedlcach
Tematy:: programmable logic array
logical synthesis
semi-custom integrated circuit
many valued gate
reducing of chip-area
Opis:: In this paper are proposed new many-valued gates K-PLA, T(2/K) and T(K/2) for a logical synthesis of digital integrated circuits. The semi-custom integrated circuit K-PLA has the architecture of a Programmable Logic Array of a type AND-OR and includes new K-valued valves MAX, MIN and GATE(A,j). A gate T(2/K) ( T(K/2)) is intended for transformation binary (K-valued ) entrance words into K-valued (binary) output words. The method of the logical synthesis with the use K-PLA, T(2/K) and T(K/2) allows to reduce nearly three times the chip-area, which is essential for placing of the circuit’s realization of the system of partial Boolean functions .
Źródło:: Studia Informatica : systems and information technology; 2007, 1(8); 7-17
1731-2264
Pojawia się w:: Studia Informatica : systems and information technology
Dostawca treści:: Biblioteka Nauki

Artykuł

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