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    Wyświetlanie 1-5 z 5
    Tytuł:
    Algorithms for generation of Ramanujan graphs, other Expanders and related LDPC codes
    Autorzy:
    Polak, M.
    Ustimenko, V.
    Powiązania:
    https://bibliotekanauki.pl/articles/106138.pdf
    Data publikacji:
    2015
    Wydawca:
    Uniwersytet Marii Curie-Skłodowskiej. Wydawnictwo Uniwersytetu Marii Curie-Skłodowskiej
    Tematy:
    Ramanujan graphs
    LDPC codes
    Opis:
    Expander graphs are highly connected sparse finite graphs. The property of being an expander seems significant in many of these mathematical, computational and physical contexts. For practical applications it is very important to construct expander and Ramanujan graphs with given regularity and order. In general, constructions of the best expander graphs with a given regularity and order is no easy task. In this paper we present algorithms for generation of Ramanujan graphs and other expanders. We describe properties of obtained graphs in comparison to previously known results. We present a method to obtain a new examples of irregular LDPC codes based on described graphs and we briefly describe properties of this codes.
    Źródło:
    Annales Universitatis Mariae Curie-Skłodowska. Sectio AI, Informatica; 2015, 15, 2; 14-21
    1732-1360
    2083-3628
    Pojawia się w:
    Annales Universitatis Mariae Curie-Skłodowska. Sectio AI, Informatica
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    LDPC codes based on algebraic graphs
    Autorzy:
    Polak, M.
    Ustimenko, V.
    Powiązania:
    https://bibliotekanauki.pl/articles/106289.pdf
    Data publikacji:
    2012
    Wydawca:
    Uniwersytet Marii Curie-Skłodowskiej. Wydawnictwo Uniwersytetu Marii Curie-Skłodowskiej
    Tematy:
    algebraic graph
    LDPC codes
    MAP decoder
    Opis:
    In this paper we investigate correcting properties of LDPC codes obtained from families of algebraic graphs. The graphs considered in this article come from the infinite incidence structure. We describe how to construct these codes, choose the parameters and present several simulations, done by using the MAP decoder. We describe how error correcting properties are dependent on the graph structure. We compare our results with the currently used codes, obtained by Guinand and Lodge [1] from the family of graphs D(k; q), which were constructed by Ustimenko and Lazebnik [2].
    Źródło:
    Annales Universitatis Mariae Curie-Skłodowska. Sectio AI, Informatica; 2012, 12, 3; 107-119
    1732-1360
    2083-3628
    Pojawia się w:
    Annales Universitatis Mariae Curie-Skłodowska. Sectio AI, Informatica
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipeline processing in low-density parity-check codes hardware decoder
    Autorzy:
    Sułek, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/202316.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    channel coding
    LDPC codes
    iterative decoding
    decoder implementation
    pipelined processing
    Opis:
    Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation – and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2011, 59, 2; 149-155
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    WiMAX Cell Level Simulation Platform Based on ns-2 and DSP Integration
    Autorzy:
    Flizikowski, A.
    Kozik, R.
    Gierszal, H.
    Przybyszewski, M.
    Hołubowicz, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/226960.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    FEC codes
    nb-LDPC
    DSP
    integrated platform
    ns-2
    Opis:
    The WiMAX (Worldwide Interoperability for Microwave Access) system based on the IEEE 802.16 family of standards is a promising technology for last-mile access. Both IEEE 802.16 and 3GPP-LTE systems candidate for becoming the 4G network of choice. The need to evaluate multiple performance enhancing techniques like MIMO, OFDM(A), novel channel coding schemes like non-binary LDPC codes, together with development of standards like IEEE 802.21, that aims at enabling handover and interoperability between heterogeneous network types, make rapid prototyping-based simulations an important issue. This paper presents a novel approach to 4G-oriented simulation environment that integrates popular network simulator (ns-2) and a Digital Signal Processing (DSP) to enable comprehensive link layer and cell level simulations. Proposed simulation environment is intended as an evaluation platform for assessing QoS/QoE and Connection Admission Control (CAC) algorithms designed for WiMAX systems. Moreover we study ways to improve simulation time (with focus on AWGN channel simulation) by using CUDA parallel processing technology for NVIDIA graphic cards.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 2; 169-176
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Robust Audio Watermarks in Frequency Domain
    Autorzy:
    Dymarski, P.
    Markiewicz, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/308461.pdf
    Data publikacji:
    2014
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    annotation watermarking
    audio watermarking
    digital signature
    dirty paper codes
    LDPC
    Opis:
    In this paper an audio watermarking technique is presented, using log-spectrum, dirty paper codes and LDPC for watermark embedding. This technique may be used as a digital communication channel, transmitting data at about 40 b/s. It may be also applied for hiding a digital signature, e.g., for copyright protection purposes. Robustness of the watermarks against audio signal compression, resampling and transmitting through an acoustic channel is tested.
    Źródło:
    Journal of Telecommunications and Information Technology; 2014, 2; 12-21
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

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