Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

English (EN)·Polski (PL)·Yкраїнський (UK)
Przejdź do strony domowej biblioteki Centralna Biblioteka Wojskowa Link otwiera się w nowym oknie Logo biblioteki Prolib Integro - strona głównaCentralna Biblioteka Wojskowa

Wyszukujesz frazę "Central Processing Unit" wg kryterium: Temat

  Lista filtrów
Wyrównaj
    Wyświetlanie 1-5 z 5
    Tytuł:
    Design of a CPU Heat Sink with Minichannel-Fins & its Thermal Analysis
    Autorzy:
    Arzutuğ, Mehmet Emin
    Powiązania:
    https://bibliotekanauki.pl/articles/27315656.pdf
    Data publikacji:
    2023
    Wydawca:
    Zachodniopomorski Uniwersytet Technologiczny w Szczecinie. Wydawnictwo Uczelniane ZUT w Szczecinie
    Tematy:
    CPU
    Central Processing Unit
    heat sink
    cooling
    nano fluid
    fin
    Opis:
    In this paper, the design and the thermal analysis of a tribled microprocessor cooler combining the advantages of strong swirl flow and minichannel-fins and CuO nanofluid, have been presented. It is thought that the results will contribute to the understanding of the effects of parameters on the cooling flux of the heat sink and the decline at the microprocessor temperature, as Reynolds number in the minichannels and CuO % volume fraction. The results have exhibited that the total performance of the heat sink cooled with the mixture of water–CuO-EG nanofluids increases with the increase of Re number and the %load of nanoparticles in the coolant. It has been determined that the energy withdrawn from the microprocessor was 241 times higher than the energy generated for maximum CuO load and Re number conditions. Besides, the highest temperature decrease has been measured at the maximum CuO load value and maximum Re number.
    Źródło:
    Polish Journal of Chemical Technology; 2023, 25, 3; 89--100
    1509-8117
    1899-4741
    Pojawia się w:
    Polish Journal of Chemical Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    About Implementation of IEC 61131-3 IL Function Blocks in Standard Microcontrollers
    Autorzy:
    Chmiel, M.
    Mocha, J.
    Hrynkiewicz, E.
    Polok, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/226742.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    central processing unit
    programmable logic controller
    microprocessor control
    microprogramming
    programming languages
    language operators
    Opis:
    The paper presents considerations on implementation of function blocks of the IL language, as fragments of control programs that use these blocks. Subsequently, the predefined function blocks of the IL language have been applied to implementation in a Central Processing Unit for a programmable controller based on standard microcontroller from such families as MCS-51, AVR and ARM with the Cortex-M3 core. The considerations refer to the IL language revision that is fully compliant with the IEC-61131-3 standards. The completed theoretical analysis demonstrated that the adopted method of the module description is really reasonable and offers substantial advantages as compared to direct calls of function modules already developed as subroutines. Also the executed experiments have proved the feasibility to arrange central units of programmable controllers on the basis of standard microcontrollers and such central units may be competitive to compact CPUs available on the market for typical PLCs.
    Źródło:
    International Journal of Electronics and Telecommunications; 2014, 60, 1; 42-46
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Concurrent operation of processors in the bit-byte CPU of a PLC
    Autorzy:
    Chmiel, M.
    Hrynkiewicz, E.
    Powiązania:
    https://bibliotekanauki.pl/articles/969831.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Instytut Badań Systemowych PAN
    Tematy:
    programmable logic controller
    central processing unit
    bit-byte structure of CPU
    scan time
    throughput time
    concurrent operation
    Opis:
    The paper presents some selected hardware solutions for the PLC dual processor bit-byte CPUs, which are oriented at optimised data exchange between the CPU processors. The optimisation aims at maximum utilisation of capabilities of the two-processor architecture of the CPU. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimise the situations, when one processor has to wait for the other.
    Źródło:
    Control and Cybernetics; 2010, 39, 2; 559-579
    0324-8569
    Pojawia się w:
    Control and Cybernetics
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Xilinx Virtex-4 jako platforma rozwojowa jednostek centralnych PLC
    Xilinx Virtex-4 - based PLC CPUs development platform
    Autorzy:
    Chmiel, M.
    Mocha, J.
    Hrynkiewicz, E.
    Powiązania:
    https://bibliotekanauki.pl/articles/156701.pdf
    Data publikacji:
    2011
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    programowalny sterownik logiczny PLC
    jednostka centralna
    przetwarzanie współbieżne
    układy programowalne
    FPGA
    programmable logic controller (PLC)
    central processing unit
    concurrent operation
    FPGA-field programmable gate array
    Opis:
    Artykuł prezentuje koncepcję platformy sprzętowo-programowej umożliwiającej testowanie różnych rozwiązań konstrukcyjnych jednostek centralnych sterowników programowalnych. Platforma do testowania jednostek bazuje na układzie FPGA Virtex-4 oraz opracowanym dedykowanym oprogramowaniu narzędziowym, umożliwiającym testowanie oraz badania właściwości opracowywanych jednostek. Przedstawiono wybrane dwuprocesorowe bitowo-bajtowe jednostki spotykane w literaturze, zorientowane na maksymalnie efektywne wykorzystanie obydwu procesorów. Szczególną uwagę zwrócono na szybkość wykonywania programu sterowania oraz funkcjonalność jednostki.
    To develop fast central processing units (CPUs) of programmable logic controllers (PLC) one can employ the architecture with two processors: a bit and a byte processor. The bit processor shall be responsible for processing the bit variables, while the byte processor shall be meant to deal with the byte (word) variables [1, 2, 3, 4, 5, 6]. In case of the double-processor architecture it is extremely important to synchronize operation of data exchange between the processors. The literature references report various synchronization methods [9, 10, 11, 12] that are described in Section 3. Sections 4 and 5 outline the combined hardware and software platform intended to enable testing and comparison between various architectures of CPUs. The presented solution employs a programmable FPGA module from the Virtex-4 family [7, 8], that are described in Section 2. The newly developed software enables compilation of application programs dedicated for the presented architecture. To develop programs for the presented solution the authors used the assembler-type programming language very similar to STL language that is normally applicable to STL controllers from Siemens [13, 14]. The software developed for PC computers make it possible to define new instructions for processors both on hardware and software levels (Fig. 1). The presented solution takes advantage of components that are typical for FPGA modules, such as BockRAM memory units (Fig. 2). The presented platforms enable further research and development efforts intended to design fast CPUs for programmable logic controllers.
    Źródło:
    Pomiary Automatyka Kontrola; 2011, R. 57, nr 1, 1; 55-57
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine
    Autorzy:
    Mahendra, H. N.
    Mallikarjunaswamy, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/2134051.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    support vector machine
    SVM
    central processing unit
    CPU
    digital signal processor
    DSP
    field programmable gate array
    FPGA
    high level synthesis
    HLS
    hardware description language
    HDL
    Opis:
    This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 3; 609--617
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

      Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies