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    Wyświetlanie 1-6 z 6
    Tytuł:
    Some Contraction Methods for Locating and Finding All the DC Operating Points of Diode-Transistor Circuits
    Autorzy:
    Tadeusiewicz, M.
    Hałgas, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/226838.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    computational methods
    DC solutions
    diodetransistor
    circuits
    multiple solutions
    Opis:
    The paper is focused on the analysis of diodetransistor circuits having multiple DC solutions (operating points) and brings two methods enabling us to find all the solutions. The first method contracts and eliminates some hyperrectangular regions where the solutions are sought. It is based on the idea of framing of the nonlinear functions appearing in the mathematical description of the circuit by linear ones and exploits the Woodbury formula in matrix theory. The other method finds quickly and easily preliminary bounds on the location of all the solutions. The method employs some monotonic functions and generates convergent sequences leading to a shrinked hyperrectangle that contains all the solutions. Both the proposed methods are rigorously proved. They constitute the core of an algorithm which efficiently finds all the DC operating points of diode-transistor circuits. It is illustrated via numerical examples.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 331-338
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multiple soft fault diagnosis of BJT circuits
    Autorzy:
    Tadeusiewicz, M.
    Hałgas, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/221281.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog circuits
    BJT circuits
    fault diagnosis
    multiple faults
    Opis:
    This paper deals with multiple soft fault diagnosis of nonlinear analog circuits comprising bipolar transistors characterized by the Ebers-Moll model. Resistances of the circuit and beta forward factor of a transistor are considered as potentially faulty parameters. The proposed diagnostic method exploits a strongly nonlinear set of algebraic type equations, which may possess multiple solutions, and is capable of finding different sets of the parameters values which meet the diagnostic test. The equations are written on the basis of node analysis and include DC voltages measured at accessible nodes, as well as some measured currents. The unknown variables are node voltages and the parameters which are considered as potentially faulty. The number of these parameters is larger than the number of the accessible nodes. To solve the set of equations the block relaxation method is used with different assignments of the variables to the blocks. Next, the solutions are corrected using the Newton-Raphson algorithm. As a result, one or more sets of the parameters values which satisfy the diagnostic test are obtained. The proposed approach is illustrated with a numerical example.
    Źródło:
    Metrology and Measurement Systems; 2014, 21, 4; 663-674
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multiple soft fault diagnosis of nonlinear dc circuits considering component tolerances
    Autorzy:
    Tadeusiewicz, M.
    Hałgas, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/221771.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog circuits
    fault diagnosis
    multiple faults
    nonlinear circuits
    Opis:
    This paper is devoted to multiple soft fault diagnosis of analog nonlinear circuits. A two-stage algorithm is offered enabling us to locate the faulty circuit components and evaluate their values, considering the component tolerances. At first a preliminary diagnostic procedure is performed, under the assumption that the non-faulty components have nominal values, leading to approximate and tentative results. Then, they are corrected, taking into account the fact that the non-faulty components can assume arbitrary values within their tolerance ranges. This stage of the algorithm is carried out using the linear programming method. As a result some ranges are obtained including possible values of the faulty components. The proposed approach is illustrated with two numerical examples.
    Źródło:
    Metrology and Measurement Systems; 2011, 18, 3; 349-360
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A fault verification method for testing of analogue electronic circuits
    Autorzy:
    Tadeusiewicz, M.
    Hałgas, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/221477.pdf
    Data publikacji:
    2018
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analogue circuits
    multiple-fault diagnosis
    Powell's method
    verification technique
    Opis:
    The paper deals with multiple soft fault diagnosis of analogue circuits. A method for diagnosis of linear circuits is developed, belonging to the class of the fault verification techniques. The method employs a measurement test performed in the frequency domain, leading to the nonlinear least squares problem. To solve this problem the Powell minimization method is applied. The diagnostic method is adapted to real circumstances, taking into account deviations of fault-free parameters and measurement uncertainty. Two examples of electronic circuits encountered in practice demonstrate that the method is efficient for diagnosis of middle-sized circuits. Although the method is dedicated to linear circuits it can be adapted to multiple soft fault diagnosis of nonlinear ones. It is illustrated by an example of a CMOS circuit designed in a sub-micrometre technology.
    Źródło:
    Metrology and Measurement Systems; 2018, 25, 2; 331-346
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A Verification Technique for Multiple Soft Fault Diagnosis of Linear Analog Circuits
    Autorzy:
    Tadeusiewicz, M.
    Ossowski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/227002.pdf
    Data publikacji:
    2018
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog circuits
    fault diagnosis
    linear circuits
    multiple soft fault
    verification technique
    Opis:
    The paper deals with multiple soft fault diagnosis of linear analog circuits. A fault verification method is developed that allows estimating the values of a set of the parameters considered as potentially faulty. The method exploits the transmittance of the circuit and is based on a diagnostic test leading to output signal in discrete form. Applying Z-transform a diagnostic equation is written which is next reproduced. The obtained system of equations consisting of larger number of equations than the number of the parameters is solved using appropriate numerical approach. The method is adapted to real circumstances taking into account scattering of the fault-free parameters within their tolerance ranges and some errors produced by the method. In consequence, the results provided by the method have the form of ranges including the values of the tested parameters. To illustrate the method two examples of real electronic circuits are given.
    Źródło:
    International Journal of Electronics and Telecommunications; 2018, 64, 1; 83-89
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    New Aspects of Fault Diagnosis of Nonlinear Analog Circuits
    Autorzy:
    Tadeusiewicz, M.
    Hałgas, S.
    Kuczyński, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226274.pdf
    Data publikacji:
    2015
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog circuits
    fault diagnosis
    local and global diagnosis
    multiple soft fault
    nonlinear circuits
    single hard faults
    Opis:
    The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits having multiple DC operating points. To solve these problems several methods have been recently developed, which employ different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated. All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits. To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke’s algorithm are employed. For illustration four numerical examples are given.
    Źródło:
    International Journal of Electronics and Telecommunications; 2015, 61, 1; 83-93
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-6 z 6

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