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    Wyświetlanie 1-4 z 4
    Tytuł:
    Low-cost hardware implementations of Salsa20 stream cipher in programmable devices
    Autorzy:
    Sugier, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/2069359.pdf
    Data publikacji:
    2013
    Wydawca:
    Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
    Tematy:
    FPGA
    stream cipher
    hardware implementation
    pipelining
    iterative architecture
    Opis:
    Salsa20 is a 256-bit stream cipher that has been proposed to eSTREAM, ECRYPT Stream Cipher Project, and is considered to be one of the most secure and relatively fastest proposals. This paper describes hardware implementation of various architectures of this cipher in popular Field Programmable Gate Arrays (FPGA). The implemented architectures are based on the loop-unrolled data flow organization and after pipelining they can reach the throughput in the range of 20 – 30 Gbps even after fully automatic implementation in popular low-cost families of Spartan-3 and Spartan-6 from Xilinx. More resource-limited iterative architectures achieve speed of 1 – 2 Gbps. The results that are included in this work present potential of the algorithm when it is implemented in a specific FPGA environment and provide some information for evaluation of cipher effectiveness in contemporary popular programmable devices.
    Źródło:
    Journal of Polish Safety and Reliability Association; 2013, 4, 1; 121--128
    2084-5316
    Pojawia się w:
    Journal of Polish Safety and Reliability Association
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms
    Autorzy:
    Sugier, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/2069086.pdf
    Data publikacji:
    2015
    Wydawca:
    Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
    Tematy:
    block cipher
    hash function
    hardware implementation
    loop unrolling
    pipelining
    FPGA
    Opis:
    The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.
    Źródło:
    Journal of Polish Safety and Reliability Association; 2015, 6, 2; 117--124
    2084-5316
    Pojawia się w:
    Journal of Polish Safety and Reliability Association
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Implementation of symmetric block ciphers in popular-grade FPGA devices
    Autorzy:
    Sugier, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/2069285.pdf
    Data publikacji:
    2012
    Wydawca:
    Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
    Tematy:
    cryptographic processor
    AES
    Serpent cipher
    hardware implementation
    pipelining
    iterative architecture
    Opis:
    In this paper we discuss hardware implementations of the two best ciphers in the AES contest – the winner Rijndael and the Serpent – in low-cost, popular Field-Programmable Gate Arrays (FPGA). After presenting the elementary operations of the ciphers and organization of their processing flows we concentrate on specific issues of their implementations in two selected families of popular-grade FPGA devices from Xilinx: currently the most common Spartan-6 and its direct predecessor Spartan-3. The discussion concentrates on differences in resources offered by these two families and on efficient implementation of the elementary transformations of the two ciphers. For case studies we propose a selection of different architectures (combinational, pipelined and iterative) for the encoding units and, after their implementation, we compare size requirements and performance parameters of the two ciphers across different architectures and on different FPGA platforms.
    Źródło:
    Journal of Polish Safety and Reliability Association; 2012, 3, 2; 179--188
    2084-5316
    Pojawia się w:
    Journal of Polish Safety and Reliability Association
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms
    Autorzy:
    Sugier, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/2068736.pdf
    Data publikacji:
    2018
    Wydawca:
    Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
    Tematy:
    hardware implementation
    loop unrolling
    pipelining
    AES
    BLAKE
    KECCAK
    SHA-3
    Opis:
    Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.
    Źródło:
    Journal of Polish Safety and Reliability Association; 2018, 9, 3; 75--84
    2084-5316
    Pojawia się w:
    Journal of Polish Safety and Reliability Association
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-4 z 4

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