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    Wyświetlanie 1-10 z 10
    Tytuł:
    On simplification of residue scaling process in pipelined Radix-4 MQRNS FFT processor
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/97551.pdf
    Data publikacji:
    2014
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    fast Fourier transform
    residue number system
    modified quadratic residue number system
    pipelined FFT processor
    Opis:
    Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent arithmetic overflow intermediate results after each butterfly have to be scaled, i.e. divided by a certain constant. The number range of the processed signal increases due to transformation of coefficients of the FFT algorithm to integers and summation and multiplication within the butterfly. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two residue scalers are needed.
    Źródło:
    Computer Applications in Electrical Engineering; 2014, 12; 588-596
    1508-4248
    Pojawia się w:
    Computer Applications in Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On configuration of residue scaling process in pipelined radix-4 MQRNS FFT processor
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/377692.pdf
    Data publikacji:
    2014
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    fast Fourier transform
    residue number system
    modified quadratic residue number system
    FFT pipelined processor
    Opis:
    Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent the arithmetic overflow in the succesive stage, every number has to be scaled, i.e. divided by a certain constant. The dynamic range of the processed signal increases due to the summation within the butterfly and the transformation of coefficients of the FFT algorithm to integers. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two scalers are needed.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2014, 80; 145-150
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
    Autorzy:
    Smyk, R.
    Ulman, Z.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/376378.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    pipelining
    residue number system
    RNS
    residue arithmetic
    Opis:
    In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 117-126
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipelined scaling of signed residue numbers with the mixed-radix conversion in the programmable gate array
    Autorzy:
    Czyżak, M.
    Smyk, R.
    Ulman, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/377373.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    scaling technique
    Mixed-Radix System
    MRS
    Residue Number System
    pipelining
    Opis:
    In this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System(MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign is detected on the basis of the value of the most significant coefficient of the MRS representation. For negative numbers their residues are adequately corrected. The basic blocks of the scaler are realized in the form of the modified two-operand modulo adders with included additional multiply and modulo reduction operations. The pipelined realization of the scaler in the Xilinx environment is shown and analyzed with respect to hardware amount and maximum pipelining frequency. The design is based on the LUTs(26x 1) that simulate small RAMs serving as the main component for the look-up realization.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 89-99
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipelined division of signed numbers with the use of residue arithmetic in FPGA
    Autorzy:
    Czyżak, M.
    Smyk, R.
    Ulman, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/97191.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    division
    multiplicative division algorithm
    scaling
    FPGA
    Opis:
    An architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length of the look-up table address, a reciprocal computation algorithm based on segmentation of the divisor into two segments is used. The signed approximate reciprocal, transformed to the residue representation, is stored in look-up tables division and multiplied by the dividend in the residue form. The obtained quotient is scaled. The pipelined realization of the divider in the FPGA environment is also shown.
    Źródło:
    Computer Applications in Electrical Engineering; 2013, 11; 455-464
    1508-4248
    Pojawia się w:
    Computer Applications in Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Ulman, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/97226.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    RNS
    scaling
    scaling algorithms
    mixed-radix system
    MRS
    FPGA
    Opis:
    A scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign of the residue number is detected by using the most significant digit of the MRS representation. Basic blocks of the scaler are realized in the form of modified two-operand modulo adders with included additional multiply and modulo reduction operations. An exemplary pipelined realization of the scaler in the Xilinx FPGA environment is shown. The design is based on Look-Up Tables (LUT)(2,sup>6 x 1) that simulate small RAMs which serve as main components for the look-up realization. Also a method is shown that allows for flexible selection of scaling factors from a set of moduli products of the RNS base. This is made by forming auxiliary MRSs by permutation of moduli of the base. All formed MRSs are associated with the given RNS with respect to the base but each MRS has different set of weights. Thus for the required scaling factor, the suitable MRS can be chosen that provides for the scaling error smaller than 1.
    Źródło:
    Computer Applications in Electrical Engineering; 2013, 11; 465-477
    1508-4248
    Pojawia się w:
    Computer Applications in Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scaling of numbers in residue arithmetic with the flexible selection of scaling factor
    Autorzy:
    Ulman, Z.
    Czyżak, M.
    Smyk, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/376813.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    scaling technique
    scaling factor
    residue arithmetic
    Residue Number System
    RNS
    Mixed-Radix System
    MRS
    Opis:
    A scaling technique of numbers in residue arithmetic with the flexible selection of the scaling factor is presented. The required scaling factor can be selected from the set of moduli products of the Residue Number System (RNS) base. By permutation of moduli of the number system base it is possible to create many auxiliary Mixed-Radix Systems (MRS). They serve as the intermediate systems in the scaling process. All MRS's are associated with the given RNS with respect to the base, but they have different sets of weights. For the scaling factor value resulting from the requirements of the given signal processing algorithm, the suitable MRS can be chosen that allows to obtain the scaling result in most simple manner.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 175-179
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    High level synthesis in FPGA of TCS/RNS converter
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/377883.pdf
    Data publikacji:
    2017
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    high–level synthesis
    residue number system
    FPGA
    C++ language
    two's complement–to–residue converter
    Opis:
    The work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is represented as the program in C++. The performed design experiments had to show whether the obtained structures of TCS/RNS converter are acceptable with respect to speed and hardware complexity. The other aim of the work was to examine whether it is enough to write the program in C++ with the use of basic arithmetic operators or bit–level description is necessary. Finally, we present the discussion of results of the TCS/RNS converter design in Xilinx Vivado HLS environment.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2017, 91; 143-154
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of a complex multiplier based on the convolution with the use of the polynomial residue number system
    Projektowanie mnożnika zespolonego oparte na splocie z użyciem wielomianowego systemu resztowego
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Ulman, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/154071.pdf
    Data publikacji:
    2007
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    cyfrowe przetwarzanie sygnałów
    mnożenie zespolone
    wielomianowy system resztowy
    digital signal processing
    complex multiplication
    polynomial residue number system
    Opis:
    The complex multiplication is one of the basic operations in digital signal processing. In this work the design procedure of the complex multiplier based on the well-known decomposition algorithm of Skavantzos and Stouraitis is presented. The algorithm makes use of encoding n-bit numbers as polynomials of degree 7 in the ring of polynomials modulo with -bit coefficients. The complex multiplication is carried out as an eight point cyclic convolution. The design procedure is illustrated by the computational example and design of a small multiplier.
    Mnożenie zespolone jest jedną z podstawowych operacji w cyfrowym przetwarzaniu sygnałów. W niniejszej pracy przestawiono metodę projektowania mnożników zespolonych opartą na znanym algorytmie dekompozycji Skavantzosa and Stouraitisa. W algorytmie tym stosuje się kodowanie liczb n-bitowych jako wielomianów stopnia 7 w pierścieniu wielomianów modulo ze współczynnikami -bitowymi. Mnożenie zespolone jest następnie realizowane jako 8-punktowy splot cykliczny. Proponowaną metodę projektowania zilustrowano przykładem obliczeniowym oraz przykładowym projektem mnożnika.
    Źródło:
    Pomiary Automatyka Kontrola; 2007, R. 53, nr 4, 4; 68-71
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    RNS/TCS converter design using high-level synthesis in FPGA
    Wysokopoziomowa synteza konwertera RNS/U2 w FPGA
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/269200.pdf
    Data publikacji:
    2017
    Wydawca:
    Politechnika Gdańska. Wydział Elektrotechniki i Automatyki
    Tematy:
    Residue Number System
    RNS
    two's-complement system
    TCS
    Chinese Remainder Theorem I
    CRT I
    FPGA
    system resztowy
    system z uzupełnieniem do 2
    U2
    konwerter RNS/U2
    chińskie twierdzenie o resztach
    Opis:
    An experimental high-level synthesis (HLS) of the residue number system (RNS) to two’s-complement system (TCS) converter in the Vivado Xilinx FPGA environment is shown. The assumed approach makes use of the Chinese Remainder Theorem I (CRT I). The HLS simplifies and accelerates the design and implementation process, moreover the HLS synthesized architecture requires less hardware by about 20% but the operational frequency is smaller by 30% than that for the VHDL designed converter.
    W pracy przedstawiono eksperymentalną wysokopoziomową syntezę w FPGA konwertera L systemu resztowego do systemu reprezentacji z uzupełnieniem do 2 (U2). W zastosowanym podejściu wykorzystano algorytm konwersji na bazie chińskiego twierdzenia o resztach (CRT 1), Zauważono, że synteza wysokopoziomowa ułatwia proces projektowania oraz zauważalnie skraca czas testowania układu. Zaprojektowana architektura konwertera przy wykorzystaniu syntezy wysokopoziomowej pochłania o około 20% zasobów układu FPGA mniej niż dla konwertera zaprojektowanego przy użyciu języka VHDL, jednak maksymalna częstotliwość pracy jest niższa o około 30%.
    Źródło:
    Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej; 2017, 57; 121-126
    1425-5766
    2353-1290
    Pojawia się w:
    Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-10 z 10

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