- Tytuł:
- Designing Method of Compact n-to-2ⁿ Decoders
- Autorzy:
-
Brzozowski, I.
Zachara, Ł.
Kos, A. - Powiązania:
- https://bibliotekanauki.pl/articles/226116.pdf
- Data publikacji:
- 2013
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
decoder
address decoder
standard cell
layouts design
CMOS technology
power dissipation
power consumption
delay - Opis:
- What decoder is, everyone knows. The paper presents fast and efficient method of layouts design of n-to-2ⁿ -lines decoders. Two scenarios of layout arrangement are proposed and described. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library. Moreover, some important parameters, such area, power dissipation and delay, were assessed and compared for decoders designed with proposed method and traditional. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. All designs were done in UMC 180 CMOS technology.
- Źródło:
-
International Journal of Electronics and Telecommunications; 2013, 59, 4; 405-413
2300-1933 - Pojawia się w:
- International Journal of Electronics and Telecommunications
- Dostawca treści:
- Biblioteka Nauki
Artykuł