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Wyszukujesz frazę "Kania, M. M." wg kryterium: Autor


Wyświetlanie 1-5 z 5
Tytuł:
Technology mapping oriented to adaptive logic modules
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/200466.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
decomposition
logic synthesis
technology mapping
ALM
Opis:
This paper presents an innovative method of technology mapping of the circuits in ALM appearing in FPGA devices by Intel. The essence of the idea is based on using triangle tables that are connected with different configurations of blocks. The innovation of the proposed method focuses on the possibility of choosing an appropriate configuration of an ALM block, which is connected with choosing an appropriate decomposition path. The effectiveness of the proposed technique of technology mapping is proved by experiments conducted on combinational and sequential circuits.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2019, 67, 5; 947-956
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Area-oriented technology mapping for LUT-based logic blocks
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/331370.pdf
Data publikacji:
2017
Wydawca:
Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:
SMTBDD
FPGA
synthesis method
decomposition technique
metoda syntezy
technika rozkładu
Opis:
One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.
Źródło:
International Journal of Applied Mathematics and Computer Science; 2017, 27, 1; 207-222
1641-876X
2083-8492
Pojawia się w:
International Journal of Applied Mathematics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
SMTBDD : New Form of BDD for Logic Synthesis
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/226064.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic synthesis
SMTBDD
decomposition
technology mapping
FPGA
digital circuits
Opis:
The main purpose of the paper is to suggest a new form of BDD - SMTBDD diagram, methods of obtaining, and its basic features. The idea of using SMTBDD diagram in the process of logic synthesis dedicated to FPGA structures is presented. The creation of SMTBDD diagrams is the result of cutting BDD diagram which is the effect of multiple decomposition. The essence of a proposed decomposition method rests on the way of determining the number of necessary ‘g’ bounded functions on the basis of the content of a root table connected with an appropriate SMTBDD diagram. The article presents the methods of searching non-disjoint decomposition using SMTBDD diagrams. Besides, it analyzes the techniques of choosing cutting levels as far as effective technology mapping is concerned. The paper also discusses the results of the experiments which confirm the efficiency of the analyzed decomposition methods.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 1; 33-41
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Synteza logiczna zespołu funkcji ukierunkowana na minimalizację liczby wykorzystywanych bloków logicznych PAL w oparciu o zmodyfikowany graf wyjść
The Logic Synthesis of the Multi-Output Boolean Function Directed to PAL Logic Block Number Minimization Based on a Modified Graphs Nodes
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/156944.pdf
Data publikacji:
2011
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
synteza logiczna
graf wyjść
układ CPLD
logic synthesis
graph's nodes
CPLD structure
Opis:
W artykule przedstawiono metodę implementacji zespołu funkcji prowadzącą do ograniczenia liczby wykorzystywanych bloków PAL. Istota metody tkwi w dopasowaniu opisu zespołu funkcji do charakterystycznej cechy każdego układu CPLD, jaką jest liczba iloczynów pojedynczego bloku PAL. Metoda wykorzystuje graf wyjść w zmodyfikowanej postaci, zawierający informacje na temat stopnia wykorzystania iloczynów w strukturze PAL. Wyniki eksperymentów wskazują, że wykorzystanie zmodyfikowanego grafu wyjść w procesie syntezy prowadzi do efektywniejszego wykorzystania zasobów struktury CPLD, w stosunku do metod implementacji opartych na klasycznym grafie wyjść.
The article is concerned with the implementation method of the multi-output Boolean function that leads to the limitation of the number of the PAL (Programmable Array Logic) logic blocks used. The essence of this technique is to match the description of a multi-output function to the distinctive feature of an each CPLD (Complex Programmable Logic Device) structure which is the number of terms of a single PAL block. This distinctive feature of a PAL block is best illustrated in the form of a picture (see Fig. 1) in which the number of terms is marked as k. Apart from that, the main purpose of the method is to apply a modified graph of outputs to present the degree to which terms were used in a given PAL block. In this article, the authors also present the operations of pasting and splitting in a modified graph of outputs thanks to which the degree of the terms used can be significantly improved. The process is presented in the form of three pictures (see Fig. 5, Fig. 6, Fig. 7). The experimental results show that the usage of a modified graph of outputs in the synthesis process enables to use the CPLD structure in a much more effective way (see Tab. 1) than in the case of the implementation method which is based on a classical graph of outputs. In the penultimate chapter proper conclusions were drawn on the experiment basis. The article ends with a bibliography list which presents all the works used by the authors while writing.
Źródło:
Pomiary Automatyka Kontrola; 2011, R. 57, nr 7, 7; 737-740
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Decomposition of multi-output functions oriented to configurability of logic blocks
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/201673.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
BDD
decomposition
logic synthesis
technology mapping
rozkład
Synteza logiczna
Mapowanie technologii
Opis:
The main goal of the paper is to present a logic synthesis strategy dedicated to an LUT-based FPGA. New elements of the proposed synthesis strategy include: an original method of function decomposition, non-disjoint decomposition, and technology mapping dedicated to configurability of logic blocks. The aim of all of the proposed synthesis approaches is the sharing of appropriately configured logic blocks. Innovation of the methods is based on the way of searching decomposition, which relies on multiple cutting of an MTBDD diagram describing a multi-output function. The essence of the proposed algorithms rests on the method of unicoding dedicated to sharing resources, searching non-disjoint decomposition on the basis of the partition of root tables, and choosing the levels of diagram cutting that will guarantee the best mapping to complex logic blocks. The methods mentioned above were implemented in the MultiDec tool. The efficiency of the analyzed methods was experimentally confirmed by comparing the synthesis results with both academic and commercial tools.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2017, 65, 3; 317-331
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-5 z 5

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