Temat: Sigma-Delta - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool
Autorzy:: Śniatała, P.
Naumowicz, M.
Handkiewicz, A.
Szczęsny, S.
Melo, J. L. A.
Paulino, N.
Goes, J.
Powiązania:: https://bibliotekanauki.pl/articles/201254.pdf
Data publikacji:: 2015
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: sigma-delta
current comparator
CAE
komparator
Opis:: The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2015, 63, 4; 919-922
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs
Autorzy:: Abdollahvand, S.
Goes, J.
Paulino, N.
Gomes, L.
Powiązania:: https://bibliotekanauki.pl/articles/397961.pdf
Data publikacji:: 2012
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: filtr decymacyjny
filtr wielofazowy
modulator sigma-delta
field-programmable gate array
FPGA
decimation filter
Polyphase Comb filter
sigma-delta modulators
field programmable gate array (FPGA)
Opis:: This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.
Źródło:: International Journal of Microelectronics and Computer Science; 2012, 3, 4; 152-158
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Analysis and Design of a First - Order Delta-Sigma Modulator based on Ultra Incomplete Settling and Considering Non-ideal Effects
Autorzy:: Nowacki, B.
Paulino, N.
Goes, J.
Powiązania:: https://bibliotekanauki.pl/articles/397918.pdf
Data publikacji:: 2012
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:: modulator Delta-Sigma
integrator bierny
konwersja analogowo-cyfrowa
konwersja A/D
filtr S.C.
delta-sigma modulator
passive integrator
analog-to-digital conversion
A/D conversion
passive SC filter
Opis:: One of the main building blocks of a Delta-Sigma modulator (ΔΣ?) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣcircuit based on the implementation of passive switched-capacitor (SC) integrator using ultra incomplete settling. The behavior of a 1st order ΔΣ? is fully analyzed and explained, as well as its non-ideal effects, which become more significant for higher clock frequencies. This work compares performance of ΔΣM clocked with Fclk=100 MHz and Fclk=300 MHz. Electrical simulations show that the ΔΣM (Fclk=300 MHz) achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 67.5 dB, a peak signal-to-noise ratio (SNR) of 69.7 dB for a signal with a bandwidth (BW) of 400 kHz, while dissipating only 232μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 165 fJ/conv.-step (simulated).
Źródło:: International Journal of Microelectronics and Computer Science; 2012, 3, 4; 125-131
2080-8755
2353-9607
Pojawia się w:: International Journal of Microelectronics and Computer Science
Dostawca treści:: Biblioteka Nauki

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