- Tytuł:
- Pipelined architecture of a chaotic pseudo-random number generator in a Cyclone V SoC device
- Autorzy:
-
Dąbal, P.
Pełka, R. - Powiązania:
- https://bibliotekanauki.pl/articles/114371.pdf
- Data publikacji:
- 2015
- Wydawca:
- Stowarzyszenie Inżynierów i Techników Mechaników Polskich
- Tematy:
-
chaotic system
random number generators
FPGA
SoC - Opis:
- In this paper, we present a novel, optimized microarchitecture of a pseudo-random number generator (PRNG) based on the chaotic model with frequency dependent negative resistances (FDNR). The project was focused on optimization of the PRNG architecture to achieve the highest possible output throughput of the generated pseudo-random sequences. As a result we got a model of the pipelined PRNG that was implemented in Cyclone V SoC from Altera and verified experimentally. All versions of the PRNG were tested by standard statistical tests NIST SP800-22. In addition, we also provide a brief comparison with the PRNG implementation in SoC from Xilinx.
- Źródło:
-
Measurement Automation Monitoring; 2015, 61, 7; 287-289
2450-2855 - Pojawia się w:
- Measurement Automation Monitoring
- Dostawca treści:
- Biblioteka Nauki
Artykuł