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Wyszukujesz frazę "system-on-a-chip" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
Simple Wide Frequency Range Impedance Meter Based on AD5933 Integrated Circuit
Autorzy:
Chabowski, K.
Piasecki, T.
Dzierka, A.
Nitsch, K.
Powiązania:
https://bibliotekanauki.pl/articles/221804.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
impedance
converter
AD5933
system-on-a-chip
measurement
Opis:
As it contains elements of complete digital impedance meter, the AD5933 integrated circuit is an interesting solution for impedance measurements. However, its use for measurements in a wide range of impedances and frequencies requires an additional digital and analogue circuitry. This paper presents the design and performance of a simple impedance meter based on the AD5933 IC. Apart from the AD5933 IC it consists of a clock generator with a programmable prescaler, a novel DC offset canceller for the excitation signal based on peak detectors and a current to voltage converter with switchable conversion ratios. The authors proposed a simple method for choosing the measurement frequency to minimalize errors resulting from the spectral leakage and distortion caused by a lack of an anti-aliasing filter in the DDS generator. Additionally, a novel method for the AD5933 IC calibration was proposed. It consists in a mathematical compensation of the systematic error occurring in the argument of the value returned from the AD5933 IC as a result. The performance of the whole system is demonstrated in an exemplary measurement.
Źródło:
Metrology and Measurement Systems; 2015, 22, 1; 13-24
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections
Autorzy:
Garbolino, T.
Powiązania:
https://bibliotekanauki.pl/articles/226543.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
integrated circuit interconnections
crosstalk
test pattern generator
built-in self-test
system-on-a-chip
Opis:
The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence.
Źródło:
International Journal of Electronics and Telecommunications; 2015, 61, 1; 67-75
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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