- Tytuł:
- Optimization problems in the synthesis of multiple-valued logic networks
- Autorzy:
-
Deniziak, S.
Wiśniewski, M.
Kurczyna, K. - Powiązania:
- https://bibliotekanauki.pl/articles/114046.pdf
- Data publikacji:
- 2016
- Wydawca:
- Stowarzyszenie Inżynierów i Techników Mechaników Polskich
- Tematy:
-
multiple-valued logic network
symbolic decomposition
FPGA
logic synthesis - Opis:
- The paper discusses some aspects of FPGA-oriented synthesis of multiple-valued logic (MVL) network, i.e. a network of modules connected by multiple-valued signals. MVL networks are built during high-level synthesis, as a source specification of logical systems or during re-synthesis of gate-level circuits. FPGA-oriented synthesis of MVL is based on decomposing modules into smaller ones, each fitting in one logic cell. In this paper, we show that the order, according to which the modules are decomposed, has a great influence on the efficiency of the synthesis. This paper presents the case study which demonstrates the above problem as well as some experimental results and conclusions.
- Źródło:
-
Measurement Automation Monitoring; 2016, 62, 5; 166-168
2450-2855 - Pojawia się w:
- Measurement Automation Monitoring
- Dostawca treści:
- Biblioteka Nauki
Artykuł