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    Wyświetlanie 1-15 z 15
    Tytuł:
    On simplification of residue scaling process in pipelined Radix-4 MQRNS FFT processor
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/97551.pdf
    Data publikacji:
    2014
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    fast Fourier transform
    residue number system
    modified quadratic residue number system
    pipelined FFT processor
    Opis:
    Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent arithmetic overflow intermediate results after each butterfly have to be scaled, i.e. divided by a certain constant. The number range of the processed signal increases due to transformation of coefficients of the FFT algorithm to integers and summation and multiplication within the butterfly. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two residue scalers are needed.
    Źródło:
    Computer Applications in Electrical Engineering; 2014, 12; 588-596
    1508-4248
    Pojawia się w:
    Computer Applications in Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On configuration of residue scaling process in pipelined radix-4 MQRNS FFT processor
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/377692.pdf
    Data publikacji:
    2014
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    fast Fourier transform
    residue number system
    modified quadratic residue number system
    FFT pipelined processor
    Opis:
    Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent the arithmetic overflow in the succesive stage, every number has to be scaled, i.e. divided by a certain constant. The dynamic range of the processed signal increases due to the summation within the butterfly and the transformation of coefficients of the FFT algorithm to integers. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two scalers are needed.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2014, 80; 145-150
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Residue number system (RNS)
    Autorzy:
    Sharoun, A. O.
    Powiązania:
    https://bibliotekanauki.pl/articles/376029.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    RNS
    residue arithmetic
    Opis:
    In the residue number system, a set of moduli which are independent of each other is given. An integer is represented by the residue of each modulus and the arithmetic operations are based on the residues individually. The arithmetic operations based on residue number system can be performed on various moduli independently to avoid the carry in addition, subtraction and multiplication, which is usually time consuming. However, the comparison and division are more complicated and the fraction number computation is immatured. Due to this, a residue number system is not yet popular in general-purpose computers, though it is extremely useful for digital-signal-processing applications. This thesis deals with the design, simulation and microcontroller implementation of some (residue number system based) building blocks for applications in the field of digital signal processing. The building blocks which have been studied are binary to residue converter, residue to binary converter, residue adder and residue multiplier.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 265-270
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
    Autorzy:
    Smyk, R.
    Ulman, Z.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/376378.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    pipelining
    residue number system
    RNS
    residue arithmetic
    Opis:
    In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 117-126
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multifunctional unit for reverse conversion and sign detection based on five-moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }
    Autorzy:
    Mojahed, Mohsen
    Molahosseini, Amir Sabbagh
    Zarandi, Azadeh Alsadat Emrani
    Powiązania:
    https://bibliotekanauki.pl/articles/2097893.pdf
    Data publikacji:
    2021
    Wydawca:
    Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
    Tematy:
    computer arithmetic
    residue number system
    reverse converter
    Opis:
    A high dynamic range moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3} has recently been introduced as an arithmetically balanced five-modull set for the residue number system (RNS). In order to utilize this moduli set in applications handling signed numbers, two important components are needed: a sign detector, and a signed reverse converter. However, having both of these components results in high-hardware requirements, which makes RNS impractical. This paper overcomes this problem by designing a unified unit that can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors’ knowledge, this is the first attempt to design a sign detector for a moduli set that includes a {2 n 3} moduli. In order to achieve a hardwareamenable design, we first improved the performance of the previous unsigned reverse converter for this moduli set. Then, we extracted a sign-detection method from the structure of the reverse converter. Finally, we made an unsigned reverse converter-to-sign converter through the use of the extracted sign signal from the reverse converter. The experimental results show that the proposed reverse convertor and sign detector result in improvements of 31% and 28% in area and delay, respectively, as compared to the previous unsigned reverse convertor with sign output using a comparator.
    Źródło:
    Computer Science; 2021, 22 (1); 101-121
    1508-2806
    2300-7036
    Pojawia się w:
    Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipelined division of signed numbers with the use of residue arithmetic in FPGA
    Autorzy:
    Czyżak, M.
    Smyk, R.
    Ulman, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/97191.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    division
    multiplicative division algorithm
    scaling
    FPGA
    Opis:
    An architecture of a pipelined signed residue divider for small number ranges is presented. The divider makes use of the multiplicative division algorithm where initially the reciprocal of the divisor is calculated and subsequently multiplied by the dividend. The divisor represented in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to reduce the needed length of the look-up table address, a reciprocal computation algorithm based on segmentation of the divisor into two segments is used. The signed approximate reciprocal, transformed to the residue representation, is stored in look-up tables division and multiplied by the dividend in the residue form. The obtained quotient is scaled. The pipelined realization of the divider in the FPGA environment is also shown.
    Źródło:
    Computer Applications in Electrical Engineering; 2013, 11; 455-464
    1508-4248
    Pojawia się w:
    Computer Applications in Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scaled residue reverse converter for signed numbers with low cost moduli base
    Autorzy:
    Czyżak, Maciej
    Smyk, Robert
    Powiązania:
    https://bibliotekanauki.pl/articles/376503.pdf
    Data publikacji:
    2019
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    residue reverse conversion
    scaling
    low-cost moduli
    Opis:
    The paper presents a realization of the scaled residue reverse converter for the low cost moduli base {2n -1,2n ,2n+1} . The moduli of this type allow for the memoryless reverse conversion using the Chinese Remainder Theorem because the orthogonal projections can be obtained by shifts and additions. Moreover, the modulo reduction of the sum of projections and sign detection algorithms are shown. Also the converter architecture is presented.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2019, 98; 101-114
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Ulman, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/97226.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    RNS
    scaling
    scaling algorithms
    mixed-radix system
    MRS
    FPGA
    Opis:
    A scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign of the residue number is detected by using the most significant digit of the MRS representation. Basic blocks of the scaler are realized in the form of modified two-operand modulo adders with included additional multiply and modulo reduction operations. An exemplary pipelined realization of the scaler in the Xilinx FPGA environment is shown. The design is based on Look-Up Tables (LUT)(2,sup>6 x 1) that simulate small RAMs which serve as main components for the look-up realization. Also a method is shown that allows for flexible selection of scaling factors from a set of moduli products of the RNS base. This is made by forming auxiliary MRSs by permutation of moduli of the base. All formed MRSs are associated with the given RNS with respect to the base but each MRS has different set of weights. Thus for the required scaling factor, the suitable MRS can be chosen that provides for the scaling error smaller than 1.
    Źródło:
    Computer Applications in Electrical Engineering; 2013, 11; 465-477
    1508-4248
    Pojawia się w:
    Computer Applications in Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An efficient implementation of the Chinese Remainder Theorem in minimally redundant Residue Number System
    Autorzy:
    Selianinau, Mikhail
    Powiązania:
    https://bibliotekanauki.pl/articles/1839284.pdf
    Data publikacji:
    2020
    Wydawca:
    Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
    Tematy:
    residue number system
    Chinese remainder theorem
    residue code
    rank of a number
    positional characteristics
    Opis:
    The Chinese Remainder Theorem (CRT) widely used in many modern computer applications. This paper presents an efficient approach to the calculation of the rank of a number, a principal positional characteristic used in the Residue Number System (RNS). The proposed method does not use large modulo addition operations compared to a straightforward implementation of the CRT algorithm. The rank of a number is equal to a sum of an inexact rank and a two-valued correction factor that only takes on the values 0 or 1. We propose a minimally redundant RNS, which provides low computational complexity of the rank calculation. The effectiveness of the novel method is analyzed concerning conventional non-redundant RNS. Owing to the extension of the residue code, by adding the extra residue modulo 2, the complexity of rank calculation goes down from \(O(k^2)\) to \(O(k)\), where \(k\) equals the number of residues in non-redundant RNS.
    Źródło:
    Computer Science; 2020, 21 (2); 225-240
    1508-2806
    2300-7036
    Pojawia się w:
    Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    SIGN detection and signed integer comparison for three-moduli SET {2n ±1, 2n+k}
    Autorzy:
    Torabi, Zeinab
    Timarchi, Somayeh
    Powiązania:
    https://bibliotekanauki.pl/articles/2097970.pdf
    Data publikacji:
    2021
    Wydawca:
    Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
    Tematy:
    computer arithmetic
    residue number system
    signed integer comparison
    dynamic range partitioning
    Opis:
    Comparison, division, and sign detection are considered to be complicated op erations in a residue number system (RNS). A straightforward solution is to convert RNS numbers into binary formats and then perform complicated op erations using conventional binary operators. If efficient circuits are provided for comparison, division, and sign detection, the application of RNS can be extended to those cases that include these operations. For RNS comparison in three-moduli set τ = {2 n−1, 2 n+k , 2 n+1},(0 ≤ k ≤ n), we have found only one hardware realization. In this paper, an efficient RNS comparator is proposed for moduli set τ , which employs a sign-detection method and operates more efficiently than its counterparts. The proposed sign detector and comparator utilize dynamic range partitioning (DRP), which has been recently presented for unsigned RNS comparison. The delay and cost of the proposed comparator are lower than the previous works, which makes it appropriate for RNS applications with limited delay and cost.
    Źródło:
    Computer Science; 2021, 22 (3); 387-401
    1508-2806
    2300-7036
    Pojawia się w:
    Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Hierarchical residue number systems with small moduli and simple converters
    Autorzy:
    Tomczak, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/907828.pdf
    Data publikacji:
    2011
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    arytmetyka cyfrowa
    układ cyfrowy
    resztowy system liczbowy
    digital arithmetic
    digital circuits
    residue number system
    VLSI
    Opis:
    In this paper, a new class of Hierarchical Residue Number Systems (HRNSs) is proposed, where the numbers are represented as a set of residues modulo factors of 2k š 1 and modulo 2k. The converters between the proposed HRNS and the positional binary number system can be built as 2-level structures using efficient circuits designed for the RNS (2k - 1, 2k, 2k +1). This approach allows using many small moduli in arithmetic channels without large conversion overhead. The advantages resulting from the use of the proposed HRNS depend on the possibility of factorisation of moduli [...].
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2011, 21, 1; 173-192
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The network coding method in wireless sensor networks based on residue number system
    Metoda sieciowego kodowania danych w bezprzewodowych sieciach sensorowych na podstawie systemu resztowego
    Autorzy:
    Yatskiv, V
    Powiązania:
    https://bibliotekanauki.pl/articles/324351.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Śląska. Wydawnictwo Politechniki Śląskiej
    Tematy:
    kodowanie danych
    bezprzewodowa sieć sensorowa
    system resztowy
    data coding
    wireless sensor network
    residue number system
    Opis:
    The paper presents and investigates the method of network encoding in the residue number system for usage in wireless sensor networks. The method of encoding provides increase of total network bandwidth by choosing coprime digit capacity different modules and different routes of transmission residues.
    W artykule zaproponowano i zbadano metodę kodowania sieciowego w systemie resztowym do stosowania w bezprzewodowych sieciach sensorowych. Opracowana metoda kodowania zwiększa ogólną przepustowość sieci dzięki wyborowi względnie pierwszych modułów o różnej pozycyjności i przesyłaniu reszt przez różne trasy.
    Źródło:
    Zeszyty Naukowe. Organizacja i Zarządzanie / Politechnika Śląska; 2013, 67; 135-144
    1641-3466
    Pojawia się w:
    Zeszyty Naukowe. Organizacja i Zarządzanie / Politechnika Śląska
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An improved high-speed residue-to-binary converter based on the Chinese Remainder Theorem
    Ulepszony szybki konwerter z systemu resztowego do systemu binarnego oparty na chińskim twierdzeniu o resztach
    Autorzy:
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/154069.pdf
    Data publikacji:
    2007
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    system resztowy
    konwersja z systemu resztowego do systemu binarnego
    residue number system
    residue-to-binary conversion
    Opis:
    A new high-speed residue-to-binary converter for five bit moduli based on the Chinese Remainder Theorem is presented. The orthogonal projections are computed by mapping using five-variable logic functions. The sum of projections is calculated using the Wallace tree. The output carry-save representation is partitioned into four segments in such a way that the sum of the numbers represented by the low-order segments does not exceed the Residue Number System (RNS) range M. The bits of the high-order segments are compressed by the small carry-propagate adder that in effect diminishes the size of the modulo M generator used to reduce the number represented by the high-order segments. The obtained sum is smaller than 2M, thus the effective two-operand final modulo M adder can be used. The proposed converter can be pipelined on the full-adder level.
    Zaprezentowano nową architekturę konwertera z systemu resztowego do systemu binarnego dla modułów 5-bitowych opartą na chińskim twierdzeniu o resztach. Projekcje ortogonalne określane są poprzez odczyt z pamięci ich obliczonych wartości. Pamięć symulowana jest poprzez użycie funkcji logicznych o liczbie zmiennych równej bitowej długości modułu. Suma projekcji obliczana jest przy użyciu sumatora wielooperandowego opartego na drzewie Wallace'a. Wyjściowe wektory sumy i przeniesienia są dzielone na cztery segmenty w taki sposób, że suma liczb reprezentowanych przez bity o młodszych wagach nie przekracza zakresu liczbowego systemu resztowego, M. Bity należące do segmentów o starszych wagach są dodawane w niewielkim sumatorze, co w efekcie umożliwia znaczne zmniejszenie rozmiaru generatora stosowanego do redukcji modulo M liczby reprezentowanej przez te bity. Suma otrzymana po zsumowaniu liczby reprezentowanej przez segmenty o młodszych wagach i zredukowanej liczby reprezentowanej przez segmenty starszych wagach nie przekracza 2M, co umożliwia zastosowanie efektywnego sumatora końcowego modulo M. Konwerter w proponowanej konfiguracji może pracować potokowo na poziomie pełnego sumatora.
    Źródło:
    Pomiary Automatyka Kontrola; 2007, R. 53, nr 4, 4; 72-73
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    High level synthesis in FPGA of TCS/RNS converter
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/377883.pdf
    Data publikacji:
    2017
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    high–level synthesis
    residue number system
    FPGA
    C++ language
    two's complement–to–residue converter
    Opis:
    The work presents the design process of the TCS/RNS (two's complement–to– residue) converter in Xilinx FPGA with the use of HLS approach. This new approach allows for the design of dedicated FPGA circuits using high level languages such as C++ language. Such approach replaces, to some extent, much more tedious design with VHDL or Verilog and facilitates the design process. The algorithm realized by the given hardware circuit is represented as the program in C++. The performed design experiments had to show whether the obtained structures of TCS/RNS converter are acceptable with respect to speed and hardware complexity. The other aim of the work was to examine whether it is enough to write the program in C++ with the use of basic arithmetic operators or bit–level description is necessary. Finally, we present the discussion of results of the TCS/RNS converter design in Xilinx Vivado HLS environment.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2017, 91; 143-154
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Effective residue-to-binary converter with the Chinese Remainder Theorem
    Efektywna konwersja liczb z systemu resztowego do systemu wagowego z uzyciem chińskiego twierdzenia o resztach
    Autorzy:
    Ulman, Z.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/152042.pdf
    Data publikacji:
    2003
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    cyfrowe przetwarzanie sygnałów
    szybka arytmetyka komputerowa
    resztowy system liczbowy
    digital signal processing
    fast computer arithmetic
    residue number system
    residue-to-binary converter
    Opis:
    The residue-to-binary conversion is the key operation in all digital signal processing applications that use the Residue Number System (RNS). In this work a new conversion technique based on the Chinese Remainder Theorem (CRT) for 5- and 6-bit moduli is proposed. It is especially suited for the realization with the use of binary arithmetic. the specific property of the realization with the use of binary arithmetic. The specific property of the technique is a way of calculation of the excess factor r in the CRT formula that makes possible, under certain conditions, the reduction of processed numbers from the range [0,nM) to [0,2M) where "M" is the product of moduli. This is done by replacing the calculation of "r" by the computation of the result of division of the sum of projections by a power of 2 close to M. Such approach allows for very effective hardware realization of the converter. Only small ROM`s and standard binary adders are required. Moreover, the pipelining on the Full-Adder (FA) level possible.
    Konwersja liczb z systemu resztowego do systemu binarnego jest podstawową operacją we wszystkich układach cyfrowego przetwarzania sygnałów, które wykorzystują system resztowy. W niniejszej pracy zaproponowano nowa metodę konwersji opartą o chinskie twierdzenie o resztach dla modułów 5- i 6-bitowych. Specyficzną cechą nowej metody jest sposób obliczania tzw. współczynnika pomiaru "r" w formule chińskiego twierdzenia o resztach, co umożliwia pod pewnymi warunkami, redukcję przetwarzanych liczb z zakresu [0,nM) do [0,2M). Jest to realizowane poprzez zastąpienie obliczania "r" obliczaniem rB, gdzie M jest potęgą liczby 2 bliska M. Takie podejście pozwala na bardzo efektywną sprzętową realizację konwertora. Konieczne są tylko małe pamięci typu ROM i standardowe sumatory binarne. ponadto możliwa jest realizacja potokowa z częstotliwością ograniczoną opóźnieniem sumatora 1-bitowego.
    Źródło:
    Pomiary Automatyka Kontrola; 2003, R. 49, nr 12, 12; 34-38
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-15 z 15

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