- Tytuł:
- FPGA-based bandwidth selection for kernel density estimation using high level synthesis approach
- Autorzy:
-
Gramacki, A.
Sawerwain, M.
Gramacki, J. - Powiązania:
- https://bibliotekanauki.pl/articles/201258.pdf
- Data publikacji:
- 2016
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
FPGA
high level synthesis
kernel density estimation
bandwidth selection
plug-in selector
synteza wysokiego poziomu
jądrowy estymator gęstości
wybór pasma informacyjnego - Opis:
- Field-programmable gate arrays (FPGA) technology can offer significantly higher performance at much lower power consumption than is available from single and multicore CPUs and GPUs (graphics processing unit) in many computational problems. Unfortunately, the pure programming for FPGA using hardware description languages (HDL), like VHDL or Verilog, is a difficult and not-trivial task and is not intuitive for C/C++/Java programmers. To bring the gap between programming effectiveness and difficulty, the high level synthesis (HLS) approach is promoted by main FPGA vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU architectures, but can also be successfully performed using HLS approach. In the paper we implement a bandwidth selection algorithm for kernel density estimation (KDE) using HLS and show techniques which were used to optimize the final FPGA implementation. We are also going to show that FPGA speedups, comparing to highly optimized CPU and GPU implementations, are quite substantial. Moreover, power consumption for FPGA devices is usually much less than typical power consumption of the present CPUs and GPUs.
- Źródło:
-
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 4; 821-829
0239-7528 - Pojawia się w:
- Bulletin of the Polish Academy of Sciences. Technical Sciences
- Dostawca treści:
- Biblioteka Nauki
Artykuł