Temat: LUT - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Hardware reduction for LUT-based mealy FSMs
Autorzy:: Barkalov, A.
Titarenko, L.
Mielcarek, K.
Powiązania:: https://bibliotekanauki.pl/articles/331362.pdf
Data publikacji:: 2018
Wydawca:: Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:: Mealy FSM
FPGA
LUT
partition
encoding collection
output variables
automat Mealy'ego
zbiór kodowany
zmienne wyjściowe
Opis:: A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.
Źródło:: International Journal of Applied Mathematics and Computer Science; 2018, 28, 3; 595-607
1641-876X
2083-8492
Pojawia się w:: International Journal of Applied Mathematics and Computer Science
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Improving LUT count of FPGA-based sequential blocks
Autorzy:: Barkalov, Alexander
Titarenko, Larysa
Mazurkiewicz, Małgorzata
Krzywicki, Kazimierz
Powiązania:: https://bibliotekanauki.pl/articles/2173598.pdf
Data publikacji:: 2021
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: FPGA
LUT
Mealy FSM
synthesis
structural decomposition
product terms
partition
automat Mealy'ego
synteza
rozkład strukturalny
warunki produktu
przegroda
Opis:: Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; art. no. e136728
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Improving LUT count of FPGA-based sequential blocks
Autorzy:: Barkalov, Alexander
Titarenko, Larysa
Mazurkiewicz, Małgorzata
Krzywicki, Kazimierz
Powiązania:: https://bibliotekanauki.pl/articles/2090732.pdf
Data publikacji:: 2021
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: FPGA
LUT
Mealy FSM
synthesis
structural decomposition
product terms
partition
automat Mealy'ego
synteza
rozkład strukturalny
warunki produktu
przegroda
Opis:: Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; e136728, 1--12
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

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