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Wyświetlanie 1-3 z 3
Tytuł:
Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms
Autorzy:
Sugier, J.
Powiązania:
https://bibliotekanauki.pl/articles/2069086.pdf
Data publikacji:
2015
Wydawca:
Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:
block cipher
hash function
hardware implementation
loop unrolling
pipelining
FPGA
Opis:
The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.
Źródło:
Journal of Polish Safety and Reliability Association; 2015, 6, 2; 117--124
2084-5316
Pojawia się w:
Journal of Polish Safety and Reliability Association
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms
Autorzy:
Sugier, J.
Powiązania:
https://bibliotekanauki.pl/articles/2068736.pdf
Data publikacji:
2018
Wydawca:
Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:
hardware implementation
loop unrolling
pipelining
AES
BLAKE
KECCAK
SHA-3
Opis:
Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.
Źródło:
Journal of Polish Safety and Reliability Association; 2018, 9, 3; 75--84
2084-5316
Pojawia się w:
Journal of Polish Safety and Reliability Association
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Implementing SHA-3 candidate BLAKE algorithm in Field Programmable Gate Arrays
Autorzy:
Sugier, J.
Powiązania:
https://bibliotekanauki.pl/articles/2069234.pdf
Data publikacji:
2016
Wydawca:
Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:
BLAKE algorithm
FPGA
hash function
implementation efficiency
loop unrolling
pipelining
Opis:
BLAKE is a cryptographic hash function proposed as a candidate in SHA-3 contest where he successfully qualified to the final round with other 4 candidates. Although it eventually lost to KECCAK it is still considered as a suitable solution with good cryptographic strength and great performance especially in software realizations. For these advantages BLAKE is commonly selected to be a hash function of choice in many contemporary IT systems in applications like digital signatures or message authentication. The purpose of this paper is to evaluate how the algorithm is suitable to be implemented in hardware using low-cost Field Programmable Gate Array (FPGA) devices, particularly to test how efficiently its complex internal transformations can be realized with FPGA resources when overall size of the implementation grows substantially with multiple rounds of the cipher running in parallel in hardware and capacity of the configurable array is used up to its limits. The study was made using the set of 7 different architectures with different loop unrolling factors and with optional application of pipelining, with each architecture being implemented in two popular families of FPGA devices from Xilinx. Investigation of the internal characteristic of the implementations generated by the tools helped in analysis how the fundamental mechanism of loop unrolling with or without pipelining works in case of this particular cipher.
Źródło:
Journal of Polish Safety and Reliability Association; 2016, 7, 1; 193--200
2084-5316
Pojawia się w:
Journal of Polish Safety and Reliability Association
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

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