Autor: Tkacz, A. - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Dual synthesis of Petri net based application specific logic controllers with increased safety
Autorzy:: Tkacz, J.
Bukowiec, A.
Adamski, M.
Powiązania:: https://bibliotekanauki.pl/articles/200217.pdf
Data publikacji:: 2016
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: critical safety
FPGAs
logic controllers
logic synthesis
Petri nets
verification
bezpieczeństwo krytyczne
FPGA
sterowniki logiczne
synteza logiczna
sieci Petriego
weryfikacja
Opis:: In the paper, design flow of the application specific logic controllers with increased safety by means of Petri nets is proposed. The controller architecture is based on duplicated control unit and comparison results from both units. One specification of control algorithm is used by means of Petri net for both units. The hardware duplication is obtained during dual synthesis process. This process uses two different logic synthesis methods to obtain two different hardware configurations for both control units. Additionally, the dual verification is applied to increase reliability of the control algorithm. Such design flow simplifies the process of realization of control systems with increased safety.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 3; 467-478
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA
Autorzy:: Bukowiec, A.
Tkacz, J.
Gratkowski, T.
Gidlewicz, T.
Powiązania:: https://bibliotekanauki.pl/articles/226156.pdf
Data publikacji:: 2013
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: C#
decomposition
FGPA
logic synthesis
Petri net
Opis:: In the paper an implementation of algorithm of Petri net array-based synthesis is presented. The method is based on decomposition of colored interpreted macro Petri net into subnets. The structured encoding of places in subnets is done of using minimal numbers of bits. Microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a twolevel concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. This algorithm is implemented in C# and delivered as a stand alone library.
Źródło:: International Journal of Electronics and Telecommunications; 2013, 59, 4; 317-324
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

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