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Wyświetlanie 1-15 z 22
Tytuł:
Hardware implementation of parametric algorithm for asynchronously gathered measurement data based on the FPGA technology
Autorzy:
Janowski, T.
Szworski, K.
Zając, R.
Powiązania:
https://bibliotekanauki.pl/articles/332532.pdf
Data publikacji:
2009
Wydawca:
Polskie Towarzystwo Akustyczne
Tematy:
hardware implementation
FPGA technology
hydroacoustic system
Opis:
The hydroacoustic system based on DOA estimation utilizes passive antenna composed of many hydrophones. The samples of the arriving acoustic signal must be gathered synchronously from each hydrophone. This enables to take advantage of parametric processing signals methods. These methods make possible determination of the amplitude and the phase relationship among particular hydrophones. The newest complex systems made up of many sub modules uses network solutions. In the case of Ethernet network some standards (e.g. Precision Time Protocol) are defined to enable synchronization of the data (samples) gathered from many hydrophones by the clock synchronization. When the antenna consists of few hydrophones then the special concentrator connected point-to-point to hydrophones can be utilized. This article discusses the issue related to PTP as well as concentrator based on FPGA technology, which uses simple UDP protocol. In the case of concentrator the synchronous method of the I/Q detection which not requires synchronous samples acquisition is also presented.
Źródło:
Hydroacoustics; 2009, 12; 83-90
1642-1817
Pojawia się w:
Hydroacoustics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Hardware implementation of a decision tree classifier for object recognition applications
Autorzy:
Fularz, M.
Kraft, M.
Powiązania:
https://bibliotekanauki.pl/articles/114595.pdf
Data publikacji:
2015
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
decision tree
hardware implementation
FPGA
object recognition
Opis:
Hardware implementation of a widely used decision tree classifier is presented in this paper. The classifier task is to perform image-based object classification. The performance evaluation of the implemented architecture in terms of resource utilization and processing speed are reported. The presented architecture is compact, flexible and highly scalable and compares favorably to software-only solutions in terms of processing speed and power consumption.
Źródło:
Measurement Automation Monitoring; 2015, 61, 7; 379-381
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Faster Point Scalar Multiplication on Short Weierstrass Elliptic Curves over Fp using Twisted Hessian Curves over Fp2
Autorzy:
Wroński, M.
Powiązania:
https://bibliotekanauki.pl/articles/308416.pdf
Data publikacji:
2016
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
elliptic curve cryptography
hardware implementation
twisted Hessian curves
Opis:
This article shows how to use fast Fp2 arithmetic and twisted Hessian curves to obtain faster point scalar multiplication on elliptic curve ESW in short Weierstrass form over Fp. It is assumed that p and #ESW(Fp) are different large primes, #E(Fq) denotes number of points on curve E over field Fq and #Et SW (Fp), where Et is twist of E, is divisible by 3. For example this method is suitable for two NIST curves over Fp: NIST P-224 and NIST P-256. The presented solution may be much faster than classic approach. Presented solution should also be resistant for side channel attacks and information about Y coordinate should not be lost (using for example Brier-Joye ladder such information may be lost). If coefficient A in equation of curve ESW : y2 =x3+Ax+B in short Weierstrass curve is not of special form, presented solution is up to 30% faster than classic approach. If A=−3, proposed method may be up to 24% faster.
Źródło:
Journal of Telecommunications and Information Technology; 2016, 3; 98-102
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design and implementation of improved sliding mode controller on 6R manipulator
Autorzy:
Korayem, M. H.
Nekoo, S. R.
Khademi, A.
Abdollahi, F.
Powiązania:
https://bibliotekanauki.pl/articles/280702.pdf
Data publikacji:
2017
Wydawca:
Polskie Towarzystwo Mechaniki Teoretycznej i Stosowanej
Tematy:
improved sliding mode control
chattering
DLCC
hardware implementation
Opis:
In this work, we present an improved sliding mode control (ISMC) technique designed and implemented for control of 6R manipulator. Sliding mode control (SMC) is a well-known nonlinear robust method for controlling systems in the presence of uncertainties and disturbances and systems with complex dynamics as in manipulators. Despite this good property, it is difficult to implement this method for the manipulator with a complex structure and more than three degree-of-freedom because of the complicated and massive equation and chattering phenomenon as a property of SMC in control inputs. Here, the chattering phenomenon is eliminated by using an effective algorithm called ISMC and implemented to 6R manipulator by using a low-cost control board based on an ARM microcontroller with high accuracy and memory. The carrying load is considered as the uncertainty for the manipulator, while the dynamic load carrying capacity (DLCC) is considered as a robot performance criterion showing robustness of the controller. The results of simulations and experiments show that the proposed approach has a good performance and is suitable and practical to be applied for manipulators.
Źródło:
Journal of Theoretical and Applied Mechanics; 2017, 55, 1; 265-280
1429-2955
Pojawia się w:
Journal of Theoretical and Applied Mechanics
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Hardware implementation of the Hough Techniques for Irregular Colour and Grey-level Pattern Recognition
Autorzy:
Żorski, W.
Żak, A.
Turner, M.
Powiązania:
https://bibliotekanauki.pl/articles/273196.pdf
Data publikacji:
2002
Wydawca:
Wojskowa Akademia Techniczna im. Jarosława Dąbrowskiego
Tematy:
Hough transform
computer vision
hardware implementation
irregular patterns
Opis:
This paper presents a hardware implementation of the Hough technique applied to the tasks of irregular colour and grey-level pattern recognition. The presented method is based on the Hough Transform with a parameter space defined by translation, rotation and scaling operations. An essential element of this method is the generalisation of the Hough Transform for grey level and colour images. The technique simplifies the application of the Hough Transform to irregular patterns recognition tasks. The hardware implementation accelerates the calculations considerably and may be used in computer vision systems, for example, in a robotic system.
Źródło:
Biuletyn Instytutu Automatyki i Robotyki; 2002, R. 8, nr 17, 17; 25-43
1427-3578
Pojawia się w:
Biuletyn Instytutu Automatyki i Robotyki
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Implementacja standardu szyfrowania AES w układzie FPGA dla potrzeb sprzętowej akceleracji obliczeń
The AES ciper standard implementation on FPGA for hardware accelerated computing
Autorzy:
Gielata, A.
Russek, P.
Wiatr, K.
Powiązania:
https://bibliotekanauki.pl/articles/152602.pdf
Data publikacji:
2007
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
Rijndael
AES
implementacja sprzętowa
FPGA
hardware implementation
Opis:
Tematem artykułu jest implementacja standardu szyfrowania danych AES-128 w układach reprogramowalnych FPGA. W systemach, gdzie wymagana jest duża szybkość szyfrowania informacji implementacje programowe okazują się zbyt wolne. W związku z tym zachodzi konieczność sprzętowej akceleracji obliczeń, a idealnym rozwiązaniem jest wykorzystanie do tego celu możliwości, jakie dają układy reprogramowalne FPGA. Do implementacji w języku VHDL wybrana została podstawowa wersja algorytmu określonego w standardzie AES. W celu uzyskania maksymalnej szybkości szyfrowania zastosowana została architektura potokowa modułu.
In this paper we investigate hardware implementation of AES-128 cipher standard on FPGA technology. In many network applications software implementations of cryptographic algorithms are slow and inefficient. To solve the problems custom architecture in reconfigurable hardware was used to speed up the performance and flexibility of Rijndael algorithm implementation. We aimed at achieving the maximum speed and efficiency of cipher process, therefore pipeline architecture of AES module was proposed. The investigations involved simulations and synthesis of VHDL code utilizing Virtex4 series of Xilinx.
Źródło:
Pomiary Automatyka Kontrola; 2007, R. 53, nr 5, 5; 48-50
0032-4140
Pojawia się w:
Pomiary Automatyka Kontrola
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
High-performance FPGA Architecture for Data Streams Processing on Example of IPsec Gateway
Autorzy:
Korona, M.
Skowron, K.
Trzepinski, M.
Rawski, M.
Powiązania:
https://bibliotekanauki.pl/articles/227331.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
IPsec
FPGA
hardware implementation
data stream processing
Opis:
In modern digital world, there is a strong demand for efficient data streams processing methods. One of application areas is cybersecurity - IPsec is a suite of protocols that adds security to communication at the IP level. This paper presents principles of high-performance FPGA architecture for data streams processing on example of IPsec gateway implementation. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 3; 351-356
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low-cost hardware implementations of Salsa20 stream cipher in programmable devices
Autorzy:
Sugier, J.
Powiązania:
https://bibliotekanauki.pl/articles/2069359.pdf
Data publikacji:
2013
Wydawca:
Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:
FPGA
stream cipher
hardware implementation
pipelining
iterative architecture
Opis:
Salsa20 is a 256-bit stream cipher that has been proposed to eSTREAM, ECRYPT Stream Cipher Project, and is considered to be one of the most secure and relatively fastest proposals. This paper describes hardware implementation of various architectures of this cipher in popular Field Programmable Gate Arrays (FPGA). The implemented architectures are based on the loop-unrolled data flow organization and after pipelining they can reach the throughput in the range of 20 – 30 Gbps even after fully automatic implementation in popular low-cost families of Spartan-3 and Spartan-6 from Xilinx. More resource-limited iterative architectures achieve speed of 1 – 2 Gbps. The results that are included in this work present potential of the algorithm when it is implemented in a specific FPGA environment and provide some information for evaluation of cipher effectiveness in contemporary popular programmable devices.
Źródło:
Journal of Polish Safety and Reliability Association; 2013, 4, 1; 121--128
2084-5316
Pojawia się w:
Journal of Polish Safety and Reliability Association
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms
Autorzy:
Sugier, J.
Powiązania:
https://bibliotekanauki.pl/articles/2069086.pdf
Data publikacji:
2015
Wydawca:
Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:
block cipher
hash function
hardware implementation
loop unrolling
pipelining
FPGA
Opis:
The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.
Źródło:
Journal of Polish Safety and Reliability Association; 2015, 6, 2; 117--124
2084-5316
Pojawia się w:
Journal of Polish Safety and Reliability Association
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Implementation of symmetric block ciphers in popular-grade FPGA devices
Autorzy:
Sugier, J.
Powiązania:
https://bibliotekanauki.pl/articles/2069285.pdf
Data publikacji:
2012
Wydawca:
Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:
cryptographic processor
AES
Serpent cipher
hardware implementation
pipelining
iterative architecture
Opis:
In this paper we discuss hardware implementations of the two best ciphers in the AES contest – the winner Rijndael and the Serpent – in low-cost, popular Field-Programmable Gate Arrays (FPGA). After presenting the elementary operations of the ciphers and organization of their processing flows we concentrate on specific issues of their implementations in two selected families of popular-grade FPGA devices from Xilinx: currently the most common Spartan-6 and its direct predecessor Spartan-3. The discussion concentrates on differences in resources offered by these two families and on efficient implementation of the elementary transformations of the two ciphers. For case studies we propose a selection of different architectures (combinational, pipelined and iterative) for the encoding units and, after their implementation, we compare size requirements and performance parameters of the two ciphers across different architectures and on different FPGA platforms.
Źródło:
Journal of Polish Safety and Reliability Association; 2012, 3, 2; 179--188
2084-5316
Pojawia się w:
Journal of Polish Safety and Reliability Association
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Some Schemes for Implementation of Arithmetic Operations with Complex Numbers Using Squaring Units
Autorzy:
Cariow, A.
Cariowa, G.
Powiązania:
https://bibliotekanauki.pl/articles/114347.pdf
Data publikacji:
2017
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
complex number arithmetic
squaring unit
implementation complexity reduction
hardware implementation
Opis:
In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence of some number of general-purpose binary multipliers. The advantage of our solutions is a removing of multiplications through replacing them by less costly squarers. We use Logan's trick and quarter square technique, which propose to replace the calculation of the product of two real numbers by summing the squares. Replacing usual multipliers with digital squares implies the reducing power consumption as well as decreases the complexity of the hardware circuit. The squarer requiring less area and power as compared to general-purpose multiplier, it is interesting to assess the use of squarers to implementation of complex arithmetic.
Źródło:
Measurement Automation Monitoring; 2017, 63, 6; 209-211
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms
Autorzy:
Sugier, J.
Powiązania:
https://bibliotekanauki.pl/articles/2068736.pdf
Data publikacji:
2018
Wydawca:
Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:
hardware implementation
loop unrolling
pipelining
AES
BLAKE
KECCAK
SHA-3
Opis:
Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.
Źródło:
Journal of Polish Safety and Reliability Association; 2018, 9, 3; 75--84
2084-5316
Pojawia się w:
Journal of Polish Safety and Reliability Association
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Basic Aspects of Designing a High-performance Processor Structure for Calculating a "true" Discrete Fractional Fourier Transform
Autorzy:
Cariow, A.
Majorkowska-Mech, D.
Powiązania:
https://bibliotekanauki.pl/articles/114579.pdf
Data publikacji:
2018
Wydawca:
Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Tematy:
discrete fractional Fourier transform
parallelization of computations
hardware implementation
complexity reduction
Opis:
This paper presents a basic aspects of structural design of the highperformance processor for implementation of discrete fractional Fourier transform (DFrFT). The general idea of the possibility of parallelizing the calculation of the so-called “true” discrete Fourier transform on the basis of our previously developed algorithmic approach is presented. We specifically focused only on the general aspects of the organization of the structure of such a processor, since the details of a particular implementation always depend on the implementation platform used, while the general idea of constructing the structure of the processor remains unchanged.
Źródło:
Measurement Automation Monitoring; 2018, 64, 2; 43-45
2450-2855
Pojawia się w:
Measurement Automation Monitoring
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Cmac and Its Extensions for Efficient System Modelling
Autorzy:
Szabo, T.
Horvath, G.
Powiązania:
https://bibliotekanauki.pl/articles/908287.pdf
Data publikacji:
1999
Wydawca:
Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:
sieć neuronowa
implementacja sprzętowa
budowle hydrotechniczne
CMAC
neural networks
hardware implementation
Opis:
This paper deals with the family of CMAC neural networks. The most important properties of this family are the extremely fast learning capability and a special architecture that makes effective digital hardware implementation possible. The paper gives an overview of the classical binary CMAC, shows the limitations of its modelling capability, gives a critical survey of its different extensions and suggests two further modifications. The aim of these modifications is to improve the modelling capability while maintaining the possibility of an effective realization. The basic element of the first suggested hardware structure is a new matrix-vector multiplier which is based on a canonical signed digit (CSD) number representation and a distributed arithmetic. In the other version, a hierarchical network structure and a special sequential training method are proposed which can constitute a trade-off between the approximation error and generalization. The proposed versions (among them a dynamic extension of the originally static CMAC) are suitable for embedded applications where the low cost and relatively high speed operation are the most important requirements.
Źródło:
International Journal of Applied Mathematics and Computer Science; 1999, 9, 3; 571-598
1641-876X
2083-8492
Pojawia się w:
International Journal of Applied Mathematics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Problems in solving fractional differential equations in a microcontroller implementation of an FOPID controller
Autorzy:
Matusiak, Mariusz
Ostalczyk, Piotr
Powiązania:
https://bibliotekanauki.pl/articles/140935.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
fractional calculus
Grünwald-Letnikov fractional-order backward difference
FOPID
hardware implementation
Opis:
The article focuses on the fractional-order backward difference, sum, linear time-invariant equation analysis, and difficulties of the fractional calculus microcontroller implementation with regard to designing a fractional-order proportional integral derivative (FOPID) controller. In opposite to the classic proportional integral derivative (PID), the FOPID controller is defined by five independent parameters. Hence, it is more customizable and, potentially, more precise on condition that the values of fractional integration and differentiation orders are properly selected. However, a number of operations and the time required to calculate the output signal continuously increase. This can be a significant problem considering the limitations of a microcontroller, including memory size and a constant sampling time of the set-up analog-to-digital (ADC) converters. In the article, three solutions are considered, and results obtained in the experiments are presented.
Źródło:
Archives of Electrical Engineering; 2019, 68, 3; 565-577
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
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