- Tytuł:
- A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks
- Autorzy:
-
Kavitha, S.
Hashim, Fazida Hanim
Kamal, Noorfazila - Powiązania:
- https://bibliotekanauki.pl/articles/226549.pdf
- Data publikacji:
- 2019
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
EDAC
ALU
speed
block reduction
power
slew rate - Opis:
- This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.
- Źródło:
-
International Journal of Electronics and Telecommunications; 2019, 65, 2; 313-318
2300-1933 - Pojawia się w:
- International Journal of Electronics and Telecommunications
- Dostawca treści:
- Biblioteka Nauki
Artykuł